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HD74LV2GT74A の電気的特性と機能

HD74LV2GT74AのメーカーはRenesas Technologyです、この部品の機能は「Single D-type Flip Flops」です。


製品の詳細 ( Datasheet PDF )

部品番号 HD74LV2GT74A
部品説明 Single D-type Flip Flops
メーカ Renesas Technology
ロゴ Renesas Technology ロゴ 




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HD74LV2GT74A Datasheet, HD74LV2GT74A PDF,ピン配置, 機能
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HD74LV2GT74A
Single D–type Flip Flops with Preset and Clear /
CMOS Logic Level Shifter
REJ03D0146–0200Z
(Previous ADE-205-681A (Z))
Rev.2.00
Oct.17.2003
Description
The HD74LV2GT74A has independent data, preset, clear, and clock inputs Q and Q outputs in an 8 pin
package. The input data is transferred to the output at the rising edge of clock pulse CLK. The input
protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used
as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to
3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high-speed
operation is suitable for the battery powered products (e.g., notebook computers), and the low power
consumption extends the battery life.
Features
The basic gate function is lined up as Renesas uni logic series.
Supplied on emboss taping for high-speed automatic mounting.
TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C
Logic-level translate function
3.0 V CMOS logic 5.0 V CMOS logic (@VCC = 5.0 V)
1.8 V or 2.5 V CMOS logic 3.3 V CMOS logic (@VCC = 3.3 V)
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
All the logical input has hysteresis voltage for the slow transition.
Ordering Information
Part Name
Package Type
HD74LV2GT74AUSE SSOP-8 pin
Package Code
TTP-8DBV
Package
Abbreviation
US
Taping Abbreviation
(Quantity)
E (3,000 pcs/reel)
Rev.2.00, Oct.17.2003, page 1 of 1

1 Page





HD74LV2GT74A pdf, ピン配列
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HD74LV2GT74A
Pin Arrangement
CLK 1
D2
Q3
GND 4
8 VCC
7 PRE
6 CLR
5Q
(Top view)
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit Test Conditions
Supply voltage range
Input voltage range *1
Output voltage range *1, 2
VCC
VI
VO
Input clamp current
Output clamp current
Continuous output current
Continuous current through
VCC or GND
Maximum power dissipation
at Ta = 25°C (in still air) *3
IIK
IOK
IO
ICC or IGND
PT
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
±50
±25
±50
200
V
V
V Output : H or L
VCC : OFF
mA VI < 0
mA VO < 0 or VO > VCC
mA VO = 0 to VCC
mA
mW
Storage temperature
Tstg
–65 to 150
°C
Notes:
The absolute maximum ratings are values, which must not individually be exceeded, and
furthermore no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.2.00, Oct.17.2003, page 3 of 9


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HD74LV2GT74A 電子部品, 半導体
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HD74LV2GT74A
Switching Characteristics
VCC = 3.3 ± 0.3 V
Item
Symbol
Maximum clock fmax
frequency
Propagation tPLH
delay time tPHL
Setup time tsu
Hold time
Pulse width
th
tw
Ta = 25°C
Min Typ
80 140
50 90
— 7.0
— 8.0
— 9.0
— 10.0
6.0 —
5.0 —
0.5 —
6.0 —
6.0 —
Max
12.5
12.0
16.0
15.5
Ta = –40 to 85°C
Test
FROM TO
Min Max Unit Conditions (Input) (Output)
70 — MHz CL = 15 pF
45 —
CL = 50 pF
1.0 14.5 ns CL = 15 pF PRE/CLR Q or Q
1.0 14.0
CLK
1.0 18.0
1.0 17.5
CL = 50 pF PRE/CLR Q or Q
CLK
7.0 —
ns
D
5.0 —
PRE or CLR inactive
0.5 —
ns
7.0 —
ns
PRE or CLR “L”
7.0 —
CLK “H” or “L”
VCC = 5.0 ± 0.5 V
Item
Symbol
Maximum clock fmax
frequency
Propagation tPLH
delay time tPHL
Setup time tsu
Hold time
Pulse width
th
tw
Ta = 25°C
Min Typ
130 180
90 140
— 5.0
— 5.6
— 6.6
— 7.2
5.0 —
3.0 —
0.5 —
5.0 —
5.0 —
Max
7.7
7.3
9.7
9.3
Ta = –40 to 85°C
Test
FROM TO
Min Max Unit Conditions (Input) (Output)
110 —
75 —
1.0 9.0
1.0 8.5
MHz CL = 15 pF
CL = 50 pF
ns CL = 15 pF
PRE/CLR Q or Q
CLK
1.0 11.0
1.0 10.5
CL = 50 pF PRE/CLR Q or Q
CLK
5.0 —
ns
D
3.0 —
PRE or CLR inactive
0.5 —
ns
5.0 —
ns
PRE or CLR “L”
5.0 —
CLK “H” or “L”
Rev.2.00, Oct.17.2003, page 6 of 9

6 Page



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部品番号部品説明メーカ
HD74LV2GT74A

Single D-type Flip Flops

Renesas Technology
Renesas Technology


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