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HD74LV2GT240AのメーカーはRenesas Technologyです、この部品の機能は「Dual Bus Buffer Inverted」です。 |
部品番号 | HD74LV2GT240A |
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部品説明 | Dual Bus Buffer Inverted | ||
メーカ | Renesas Technology | ||
ロゴ | |||
このページの下部にプレビューとHD74LV2GT240Aダウンロード(pdfファイル)リンクがあります。 Total 9 pages
www.DataSheet4U.com
HD74LV2GT240A
Dual Bus Buffer Inverted with 3–state Output /
CMOS Logic Level Shifter
REJ03D0151–0200Z
(Previous ADE-205-678A (Z))
Rev.2.00
Oct.23.2003
Description
The HD74LV2GT240A has dual bus buffer inverted with 3–state output in an 8 pin package. Two
inverters are included in one circuit. Each circuit can be independently controlled by the enable signal 1OE
or 2OE, which enables outputs when receiving a low-level signal. The input protection circuitry on this
device allows over voltage tolerance on the input, allowing the device to be used as a logic–level translator
from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while
operating at the high-voltage power supply. Low voltage and high-speed operation is suitable for the
battery powered products (e.g., notebook computers), and the low power consumption extends the battery
life.
Features
• The basic gate function is lined up as Renesas uni logic series.
• Supplied on emboss taping for high-speed automatic mounting.
• TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C
• Logic-level translate function
3.0 V CMOS logic → 5.0 V CMOS logic (@VCC = 5.0 V)
1.8 V or 2.5 V CMOS logic → 3.3 V CMOS logic (@VCC = 3.3 V)
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V, Output : Z)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
• All the logical input has hysteresis voltage for the slow transition.
• Ordering Information
Part Name
Package Type
HD74LV2GT240AUSE SSOP-8 pin
Package Code
TTP-8DBV
Package
Abbreviation
US
Taping Abbreviation
(Quantity)
E (3,000 pcs/reel)
Rev.2.00, Oct.23.2003, page 1 of 8
1 Page www.DataSheet4U.com
HD74LV2GT240A
Pin Arrangement
1OE 1
A1 2
Y2 3
GND 4
8 VCC
7 2OE
6 Y1
5 A2
(Top view)
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit Test Conditions
Supply voltage range
Input voltage range *1
Output voltage range *1, 2
VCC
VI
VO
Input clamp current
Output clamp current
Continuous output current
Continuous current through
VCC or GND
Maximum power dissipation
at Ta = 25°C (in still air) *3
IIK
IOK
IO
ICC or IGND
PT
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
±50
±25
±50
200
V
V
V Output : H or L
VCC : OFF or output : Z
mA VI < 0
mA VO < 0 or VO > VCC
mA VO = 0 to VCC
mA
mW
Storage temperature
Tstg
–65 to 150
°C
Notes:
The absolute maximum ratings are values, which must not individually be exceeded, and
furthermore no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.2.00, Oct.23.2003, page 3 of 8
3Pages www.DataSheet4U.com
HD74LV2GT240A
Test Circuit
VCC
Input
Pulse Generator
Z OUT = 50 Ω
VCC
Output
1k Ω S1
CL =
15 or 50 pF
OPEN
*1 See under table
GND
TEST
tPLH / t PHL
tZH/ t HZ
tZL / t LZ
S1
OPEN
GND
VCC
Note: 1. CL includes probe and jig capacitance.
Rev.2.00, Oct.23.2003, page 6 of 8
6 Page | |||
ページ | 合計 : 9 ページ | ||
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PDF ダウンロード | [ HD74LV2GT240A データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
HD74LV2GT240A | Dual Bus Buffer Inverted | Renesas Technology |