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HD74LV2G74AのメーカーはRenesas Technologyです、この部品の機能は「Single D-type Flip Flops」です。 |
部品番号 | HD74LV2G74A |
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部品説明 | Single D-type Flip Flops | ||
メーカ | Renesas Technology | ||
ロゴ | |||
このページの下部にプレビューとHD74LV2G74Aダウンロード(pdfファイル)リンクがあります。 Total 9 pages
www.DataSheet4U.com
HD74LV2G74A
Single D–type Flip Flops with Preset and Clear
REJ03D0097–0500
(Previous: ADE-205-346D)
Rev.5.00
Apr 07, 2006
Description
The HD74LV2G74A has independent data, preset, clear, and clock inputs Q and Q outputs in an 8 pin package. The
input data is transferred to the output at the rising edge of clock pulse CLK. Low voltage and high-speed operation is
suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the
battery life.
Features
• The basic gate function is lined up as Renesas uni logic series.
• Supplied on emboss taping for high-speed automatic mounting.
• Electrical characteristics equivalent to the HD74LV74A
Supply voltage range : 1.65 to 5.5 V
Operating temperature range : –40 to +85°C
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
• All the logical input has hysteresis voltage for the slow transition.
• Ordering Information
Part Name
Package Type
HD74LV2G74AUSE SSOP-8 pin
Package Code
(Previous code)
PVSP0008KA-A
(TTP-8DBV)
Package
Abbreviation
US
Taping Abbreviation
(Quantity)
E (3,000 pcs / Reel)
Outline and Article Indication
• HD74LV2G74A
Index band
Lot No.
SSOP–8
YMW
L74
Y : Year code
(the last digit of year)
M : Month code
W : Week code
Marking
Rev.5.00 Apr 07, 2006 page 1 of 8
1 Page HD74LV2G74A
www.DaAtaSbhseoet4luU.tceomMaximum Ratings
Item
Symbol
Ratings
Unit Test Conditions
Supply voltage range
Input voltage range *1
Output voltage range *1, 2
VCC
VI
VO
Input clamp current
Output clamp current
Continuous output current
Continuous current through VCC or GND
Maximum power dissipation
at Ta = 25°C (in still air) *3
IIK
IOK
IO
ICC or IGND
PT
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
±50
±25
±50
200
V
V
V Output : H or L
VCC : OFF
mA VI < 0
mA VO < 0 or VO > VCC
mA VO = 0 to VCC
mA
mW
Storage temperature
Tstg –65 to 150 °C
Notes:
The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two
of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Symbol
Min
Supply voltage range
VCC 1.65
Input voltage range
VI 0
Output voltage range
VO 0
Output current
IOL —
—
—
—
IOH —
—
—
—
Input transition rise or fall rate
∆t / ∆v
0
0
0
0
Operating free-air temperature
Ta
–40
Note: Unused or floating inputs must be held high or low.
Max
5.5
5.5
VCC
1
2
6
12
–1
–2
–6
–12
300
200
100
20
85
Unit
V
V
V
mA
ns / V
°C
Conditions
VCC = 1.65 to 1.95 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 1.65 to 1.95 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 1.65 to 1.95 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
Rev.5.00 Apr 07, 2006 page 3 of 8
3Pages HD74LV2G74A
www.DataSheet4U.com
Item
Maximum clock
frequency
Propagation
delay time
Setup time
Hold time
Pulse width
Symbol
fmax
tPLH
tPHL
tsu
th
tw
Ta = 25°C
Min Typ Max
130 180 —
90 140 —
— 5.0 7.7
— 5.6 7.3
— 6.6 9.7
— 7.2 9.3
5.0 —
—
3.0 —
—
0.5 —
—
5.0 —
—
5.0 —
—
Ta = –40 to 85°C
Min Max
110 —
75 —
1.0 9.0
1.0 8.5
1.0 11.0
1.0 10.5
5.0 —
3.0 —
0.5 —
5.0 —
5.0 —
Test
Unit Conditions
VCC = 5.0 ± 0.5 V
FROM
TO
(Input) (Output)
MHz
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
PRE/CLR
CLK
Q or Q
CL = 50 pF PRE/CLR Q or Q
CLK
ns D
PRE or CLR inactive
ns
ns PRE or CLR “L”
CLK “H” or “L”
Operating Characteristics
Item
Power dissipation
capacitance
Test Circuit
Symbol
CPD
VCC (V)
3.3
5.0
Input
Pulse Generator
Zout = 50 Ω
Input
Ta = 25°C
Min Typ
— 13.0
— 14.0
VCC VCC
PRE
D
Q
Max
—
—
CL
CL = 50 pF
Unit Test Conditions
pF f = 10 MHz
Output Q
Pulse Generator
Zout = 50 Ω
CLK
CLR
Q
Output Q
CL
Notes: 1. CL includes probe and jig capacitance.
2. Test is put into the each flip flops.
Rev.5.00 Apr 07, 2006 page 6 of 8
6 Page | |||
ページ | 合計 : 9 ページ | ||
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PDF ダウンロード | [ HD74LV2G74A データシート.PDF ] |
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部品番号 | 部品説明 | メーカ |
HD74LV2G74A | Single D-type Flip Flops | Renesas Technology |
HD74LV2G74A | Single D-type Flip Flops | Hitachi Semiconductor |