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HD74LV2G240A の電気的特性と機能

HD74LV2G240AのメーカーはRenesas Technologyです、この部品の機能は「Dual Bus Buffer Inverted」です。


製品の詳細 ( Datasheet PDF )

部品番号 HD74LV2G240A
部品説明 Dual Bus Buffer Inverted
メーカ Renesas Technology
ロゴ Renesas Technology ロゴ 




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HD74LV2G240A Datasheet, HD74LV2G240A PDF,ピン配置, 機能
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HD74LV2G240A
Dual Bus Buffer Inverted with 3–state Output
REJ03D0102–0400Z
(Previous ADE-205-349C (Z))
Rev.4.00
Sep.30.2003
Description
The HD74LV2G240A has dual bus buffer inverted with 3–state output in an 8 pin package. Two inverters
are included in one circuit. Each circuit can be independently controlled by the enable signal 1OE or 2OE,
which enables outputs when receiving a low-level signal. Low voltage and high-speed operation is suitable
for the battery powered products (e.g., notebook computers), and the low power consumption extends the
battery life.
Features
The basic gate function is lined up as Renesas uni logic series.
Supplied on emboss taping for high-speed automatic mounting.
Electrical characteristics equivalent to the HD74LV240A
Supply voltage range : 1.65 to 5.5 V
Operating temperature range : –40 to +85°C
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V, Output : Z)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
All the logical input has hysteresis voltage for the slow transition.
Ordering Information
Part Name
Package Type
Package Code Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LV2G240AUSE SSOP-8 pin
TTP-8DBV
US
E (3,000 pcs/reel)
Rev.4.00, Sep.30.2003, page 1 of 9

1 Page





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HD74LV2G240A
Pin Arrangement
1OE 1
A1 2
Y2 3
GND 4
8 VCC
7 2OE
6 Y1
5 A2
(Top view)
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit Test Conditions
Supply voltage range
Input voltage range *1
Output voltage range *1, 2
VCC
VI
VO
Input clamp current
Output clamp current
Continuous output current
Continuous current through
VCC or GND
Maximum power dissipation
at Ta = 25°C (in still air) *3
IIK
IOK
IO
ICC or IGND
PT
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
±50
±25
±50
200
V
V
V Output : H or L
VCC : OFF or output : Z
mA VI < 0
mA VO < 0 or VO > VCC
mA VO = 0 to VCC
mA
mW
Storage temperature
Tstg
–65 to 150
°C
Notes:
The absolute maximum ratings are values, which must not individually be exceeded, and
furthermore no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.4.00, Sep.30.2003, page 3 of 9


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HD74LV2G240A 電子部品, 半導体
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HD74LV2G240A
Switching Characteristics
VCC = 1.8 ± 0.15 V
Item
Symbol
Propagation tPLH
delay time tPHL
Enable time tZH
tZL
Disable time tHZ
tLZ
Ta = 25°C
Min Typ
— 13.5
— 19.0
— 13.7
— 20.5
— 8.3
— 13.0
Max
23.5
33.0
26.5
36.0
20.0
29.5
Ta = –40 to 85°C Unit Test
FROM
Min Max
Conditions (Input)
1.0 26.0 ns CL = 15 pF A
1.0 36.0
CL = 50 pF
1.0 29.0 ns CL = 15 pF OE
1.0 38.0
CL = 50 pF
1.0 22.5 ns CL = 15 pF OE
1.0 32.0
CL = 50 pF
TO
(Output)
Y
Y
Y
VCC = 2.5 ± 0.2 V
Item
Symbol
Propagation tPLH
delay time tPHL
Enable time tZH
tZL
Disable time tHZ
tLZ
Ta = 25°C
Min Typ
— 6.3
— 8.2
— 7.4
— 9.5
— 5.7
— 8.1
Max
11.6
14.4
13.0
16.5
14.7
18.2
Ta = –40 to 85°C Unit Test
FROM
Min Max
Conditions (Input)
1.0 14.0 ns CL = 15 pF A
1.0 17.0
CL = 50 pF
1.0 15.5 ns CL = 15 pF OE
1.0 18.5
CL = 50 pF
1.0 17.0 ns CL = 15 pF OE
1.0 20.5
CL = 50 pF
TO
(Output)
Y
Y
Y
VCC = 3.3 ± 0.3 V
Item
Symbol
Propagation tPLH
delay time tPHL
Enable time tZH
tZL
Disable time tHZ
tLZ
Ta = 25°C
Min Typ
— 4.6
— 5.9
— 5.1
— 6.6
— 4.4
— 6.1
Max
7.5
11.0
8.0
11.5
9.7
13.2
Ta = –40 to 85°C Unit Test
FROM
Min Max
Conditions (Input)
1.0 9.0 ns CL = 15 pF A
1.0 12.5
CL = 50 pF
1.0 9.5 ns CL = 15 pF OE
1.0 13.0
CL = 50 pF
1.0 11.5 ns CL = 15 pF OE
1.0 15.0
CL = 50 pF
TO
(Output)
Y
Y
Y
Rev.4.00, Sep.30.2003, page 6 of 9

6 Page



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部品番号部品説明メーカ
HD74LV2G240A

Dual Bus Buffer Inverted

Renesas Technology
Renesas Technology


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