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PDF F25L016A Data sheet ( Hoja de datos )
| Número de pieza | F25L016A | |
| Descripción | 16Mbit (2Mx8) 3V Only Serial Flash Memory | |
| Fabricantes | Elite Semiconductor | |
| Logotipo |  |
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FEATURES
y Single supply voltage 2.7~3.6V
y Speed
- Read max frequency : 33MHz
- Fast Read max frequency : 50MHz;100MHz
y Low power consumption
- typical active current
- 15 μ A typical standby current
y Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
y Program
- Byte program time 7 μ s(typical)
y Erase
- Chip erase time 10s(typical)
- Sector erase time 60ms(typical)
F25L016A
16Mbit (2Mx8)
3V Only Serial Flash Memory
block erase time 1sec (typical)
y Auto Address Increment (AAI) WORD Programming
- Decrease total chip programming time over
Word-Program operations
y SPI Serial Interface
- SPI Compatible : Mode 0 and Mode3
y End of program or erase detection
y Write Protect ( WP )
y Hold Pin ( HOLD )
y Package available
- 8-pin SOIC 200-mil
ORDERING INFORMATION
Part No.
Speed
Package
F25L016A –50PAG 50MHz 8 lead SOIC
200mil
F25L016A –100PAG 100MHz 8 lead SOIC
200mil
COMMENTS
Pb-free
Pb-free
GENERAL DESCRIPTION
The F25L016A is a 16Megablt, 3V only CMOS Serial Flash
memory device organized as 2M bytes of 8 bits. This device is
packaged in 8-lead SOIC 200mil. ESMT’s memory devices
reliably store memory data even after 100,000 program and
erase cycles.
The F25L016A features a sector erase architecture. The device
memory array is divided into 512 uniform sectors with 4K byte
each ; 32 uniform blocks with 64K byte each. Sectors can be
erased individually without affecting the data in other sectors.
Blocks can be erased individually without affecting the data in
other blocks. Whole chip erase capabilities provide the flexibility
to revise the data in the device.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision: 1.2 1/31
1 page  
ESMTwww.DataSheet4U.com
127
7:
112
111
6:
96
95
5:
80
79
4:
64
63
3:
48
47
2:
32
31
1:
16
15
0:
0
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
F25L016A
07F000H – 07FFFFH
:
070000H – 070FFFH
06F000H – 06FFFFH
:
060000H – 060FFFH
05F000H – 05FFFFH
:
050000H – 050FFFH
04F000H – 04FFFFH
:
040000H – 040FFFH
03F000H – 03FFFFH
:
030000H – 030FFFH
02F000H – 02FFFFH
:
020000H – 020FFFH
01F000H – 01FFFFH
:
010000H – 010FFFH
00F000H – 00FFFFH
:
000000H – 000FFFH
001 1 1
001 1 0
001 0 1
001 0 0
000 1 1
000 1 0
000 0 1
000 0 0
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision: 1.2 5/31
5 Page 
ESMTwww.DataSheet4U.com
F25L016A
bottom memory type ; third byte 15H as memory capacity.
11. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other.
The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions
effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN.
Read (33 MHz)
The Read instruction supports up to 33 MHz, it outputs the data
starting from the specified address location. The data output
stream is continuous through all addresses until terminated by a
low to high transition on CE . The internal address pointer will
automatically increment until the highest memory address is
reached. Once the highest memory address is reached, the
address pointer will automatically increment to the beginning
(wrap-around) of the address space, i.e. for 16Mbit density, once
the data from address location 1FFFFFH had been read, the next
output will be from address location 00000H.
The Read instruction is initiated by executing an 8-bit command,
03H, followed by address bits [A23-A0]. CE must remain active
low for the duration of the Read cycle. See Figure 2 for the Read
sequence.
CE
MODE3
SCK MODE1
1 23 45 67 8
15 16 23 24
31 32 39 40 47 48 55 56 63 64
70
SI
03
ADD.
ADD.
ADD.
MSB
MSB
HIGH IMPENANCE
SO
N
DOU T
MSB
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
D OU T
Figure 2 : READ SEQUENCE
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision: 1.2 11/31
11 Page | ||
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| PDF Descargar | [ Datasheet F25L016A.PDF ] | |
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