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NJU8716A の電気的特性と機能

NJU8716AのメーカーはJRCです、この部品の機能は「PWM/PDM / SSOP16」です。


製品の詳細 ( Datasheet PDF )

部品番号 NJU8716A
部品説明 PWM/PDM / SSOP16
メーカ JRC
ロゴ JRC ロゴ 




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NJU8716A Datasheet, NJU8716A PDF,ピン配置, 機能
www.DataSheet4U.com
NJU8716A/B
Switching Driver with Regulator
for Class-D Headphone Amplifier
PRELIMINARY
GENERAL DESCRIPTION
The NJU8716A/B is switching driver with regulator for
class-D headphone amplifier. It incorporates optimum
regulator for the driver of headphone amplifier.
The NJU8716A/B converts 1bit audio signals such as
PWM/PDM to analog audio signals with simple external
LC low-pass filter.
The NJU8716A/B provides completed digital system
and high power-efficiency with class-D operation.
Therefore it is suitable for portable audio applications.
FEATURES
2-channel 1bit Audio Signal Input
Headphone Output
Built-in Regulator for Driver
Logic Operating Voltage
Driver Operating Voltage
Regulator Operating Voltage
C-MOS Technology
1.7~3.0V(VDD)
1.6~3.5V(VDDO1, VDDO2)
4.0~5.75V(VREG1)
1.9~4.0V(VREG2)
Package Outline
SSOP16
Version Lineup
Version
NJU8716A
NJU8716B
Data Latch
The rising edge of MCK
The falling edge of MCK
BLOCK DIAGRAM
PACKAGE OUTLINE
NJU8716AV, NJU8716BV
PIN CONFIGURATION
VREGO
CFB
VREG1
VCONT
VSS
MCK
VDD
DIN2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VREG2
VDDO2
OUT2
VSSO
VSSO
OUT1
VDDO1
DIN1
VDD
VSS
DIN1
MCK
DIN2
Low Voltage
Detector VDD
Level Shifter
Level Shifter
Level Shifter
Level Shifter
Regulator
Pre
Driver
Pre
Driver
Low Voltage
Detector VREGO
HP Amp
HP Amp
VDDO1
OUT1
VSSO
VDDO2
OUT2
VSSO
Ver.2005-03-09
-1-

1 Page





NJU8716A pdf, ピン配列
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NJUN8J7U163A55/B5
FUNCTIONAL DESCRIPTION
(1) Power Supply
VDD : Power supply for input circuit and control logic. Keep the input logic level less than VDD.
If VDD reaches less than sleep detection voltage, power consumption can be saved with halts of built-in
regulator.
VREG1 : Power supply for built-in regulator. Even after power-on, VREG1 line is shut off with transistor switch until
VDD has been started up.
VREG2 : Power supply for built-in regulator. Apply the required voltage with additional dropout voltage of
regulator. By connecting VREGO (regulator output) to VDDO1, VDDO2 (Driver power supply), the power is
provided at the drivers. And furthermore, the regulator output should be supplied to VDDO1 and VDDO2 by
connecting de-coupling capacitor to get highly smoothed power supply.
(2) Regulator Output Voltage Control Terminal (VCONT)
VCONT is the control terminal for regulator output voltage. VREGO terminal generates double the voltage of
supplied voltage to VCONT. (Shorted between VREGO-CFB)
(3) Master Clock (MCK)
Master clock (MCK) synchronizes the audio signal inputs (DIN1 and DIN2). The setup time and the hold time
should be kept in the AC characteristics because DIN1 and DIN2 are fetched with the rising edge of MCK in A
version, and the falling edge of MCK in B version. During the standby condition, MCK requires “L” level to avoid
unnecessary power consumption. In addition, MCK requires jitter-free or jitter as small as possible because the
jitter could lead to poor S/N ratio.
(4) Signal Output (OUT1 / OUT2)
OUT1 and OUT2 terminals keep the Hi-z condition if output voltage of VREGO is lower than detection voltage.
Output signals are appeared as PWM signals through the use of VDDO1 and VDDO2 in the OUT1 and OUT2
terminals If the output voltage is over than detection voltage. Output signals will be converted to analog signals
via 2nd-order or higher LC filter.
POWER ON/DOWN SEQUENCE
The pop-noise can be effectively suppressed with the following sequence when power ON and OFF.
(1) Power ON Sequence
1) Start up VDD, VREG1 and VREG2.
2) Input the master clock (MCK) and audio signals (DIN1, DIN2) after the start-up of VDD, VREG1 and VREG2.
At this time, audio signals must be input as “Sound-less data”.
3) Increase VCONT.
4) Input the audio data after VCONT reaches a steady state.
(2) Power Down Sequence
The sequence must be executed in inverse order of the power ON sequence.
VDD, VREG1, VREG2
VCONT
MCK
DIN1, DIN2
Sound-less Data
OUT1, OUT2 High impedance
Audio Data
Audio signal output
Sound-less Data
High impedance
Ver.2005-03-09
-3-


3Pages


NJU8716A 電子部品, 半導体
NJU8716A/B
www.DataSheet4U.com
(3) AC CHARACTERISTICS
PARAMETER
(Ta=25°C, VDD=2.0V, VDDO1=VDDO2=1.8V, VREG2=2.15V, VREG1=5.0V, VSS=VSSO=0.0V,
Load Impedance=16, fS=44.1kHz, unless otherwise noted)
SYMBOL
CONDITION
MIN
TYP
MAX
UNIT
MCK Frequency
fMCKI
8 - 25 MHz
MCK Pulse Width (H)
tMCKH
12 -
- ns
MCK Pulse Width (L)
tMCKL
12 -
- ns
DIN1, DIN2 Setup Time
tDS
20 -
- ns
DIN1, DIN2 Hold Time
tDH
20 -
- ns
MCK
(A Version)
MCK
(B Version)
DIN1, DIN2
tDS
tMCKH
tMCKL
tMCKL
tMCKH
tMCKI
tDH
-6-
Ver.2005-03-09

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
NJU8716A

PWM/PDM / SSOP16

JRC
JRC
NJU8716A

PWM/PDM / SSOP16

JRC
JRC
NJU8716B

PWM/PDM / SSOP16

JRC
JRC
NJU8716B

PWM/PDM / SSOP16

JRC
JRC


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