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PDF F801FA60 Data sheet ( Hoja de datos )
| Número de pieza | F801FA60 | |
| Descripción | DSP56F801FA60 | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Freescale Semiconductor, Inc.
DSP56F801/D
Rev. 13.0, 02/2004
56F801
www.datasheet4u.com
Technical Data
56F801 16-bit Hybrid Controller
• Up to 30 MIPS operation at 60MHz core
frequency
• Up to 40 MIPS operation at 80MHz core
frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
• Hardware DO and REP loops
• 6-channel PWM Module
• Two 4-channel, 12-bit ADCs
• Serial Communications Interface (SCI)
• 8K × 16-bit words Program Flash
• 1K × 16-bit words Program RAM
• 2K × 16-bit words Data Flash
• 1K × 16-bit words Data RAM
• 2K × 16-bit words Boot Flash
• Serial Peripheral Interface (SPI)
• General Purpose Quad Timer
• JTAG/OnCETM port for debugging
• On-chip relaxation oscillator
• 11 shared GPIO
• 48-pin LQFP Package
6
PWM Outputs
Fault Input
A/D1
4 A/D2 ADC
4 VREF
PWMA
RESET
IRQA
6
JTAG/
OnCE
Port
VCAPC VDD
24
VSS
5*
VDDA
VSSA
Digital Reg Analog Reg
Low Voltage
Supervisor
Interrupt
Controller
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Quad Timer C
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
Quad Timer D
Boot Flash
3
or GPIO
2048 x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
SCI0
or
2 GPIO
COP/
Watchdog
Application-
SPI Specific
4
or
GPIO
Memory &
Peripherals
••
PAB
PDB
•
XDB2
CGDB
• • •XAB1
•XAB2
•INTERRUPT
IPBB
CONTROLS CONTROLS
16 16
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
IPBus Bridge
(IPBB)
16-Bit
56800
Core
PLL
Clock Gen
or Optional
Internal
Relaxation Osc.
*includes TCS pin which is reserved for factory use and is tied to VSS
Figure 1. 56F801 Block Diagram
GPIOB3/XTAL
GPIOB2/EXTAL
© Motorola, Inc., 2004. All rights reserved.
For More Information On This Product,
Go to: www.freescale.com
1 page  
Freescale Semiconductor, Inc.
Data Sheet Conventions
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
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“asserted”
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Examples:
Signal/Symbol
Logic State
Signal State
Voltage1
PIN
True
Asserted
VIL/VOL
PIN
False
Deasserted
VIH/VOH
PIN
True
Asserted
VIH/VOH
PIN
False
Deasserted
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
VIL/VOL
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F801 are organized into functional groups, as shown in Table 2 and
as illustrated in Figure 2. In Table 3 through Table 13, each table row describes the signal or signals
present on a pin.
Table 2. Functional Group Pin Allocations
Functional Group
Power (VDD or VDDA)
Ground (VSS or VSSA)
Supply Capacitors
PLL and Clock
Interrupt and Program Control
Pulse Width Modulator (PWM) Port
Serial Peripheral Interface (SPI) Port1
Serial Communications Interface (SCI) Port1
Analog-to-Digital Converter (ADC) Port
Quad Timer Module Port
JTAG/On-Chip Emulation (OnCE)
1. Alternately, GPIO pins
Number of
Pins
5
6
2
2
2
7
4
2
9
3
6
Detailed
Description
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
56F801 Technical Data
For More Information On This Product,
Go to: www.freescale.com
5
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Freescale Semiconductor, Inc.
JTAG/OnCE
2.10 JTAG/OnCE
Table 13. JTAG/On-Chip Emulation (OnCE) Signals
No. of Signal
Pins Name
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1 TCK
1 TMS
1 TDI
1 TDO
1 TRST
1 DE
Signal State During
Type
Reset
Signal Description
Input Input, pulled Test Clock Input—This input pin provides a gated clock to
(Schmitt) low internally synchronize the test logic and shift serial data to the JTAG/OnCE port.
The pin is connected internally to a pull-down resistor.
Input Input, pulled Test Mode Select Input—This input pin is used to sequence the JTAG
(Schmitt) high internally TAP controller’s state machine. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.
Input Input, pulled Test Data Input—This input pin provides a serial input data stream to
(Schmitt) high internally the JTAG/OnCE port. It is sampled on the rising edge of TCK and has
an on-chip pull-up resistor.
Output
Tri-stated
Test Data Output—This tri-statable output pin provides a serial output
data stream from the JTAG/OnCE port. It is driven in the Shift-IR and
Shift-DR controller states, and changes on the falling edge of TCK.
Input Input, pulled Test Reset—As an input, a low signal on this pin provides a reset
(Schmitt) high internally signal to the JTAG TAP controller. To ensure complete hardware reset,
TRST should be asserted whenever RESET is asserted. The only
exception occurs in a debugging environment when a hardware device
reset is required and it is necessary not to reset the OnCE/JTAG
module. In this case, assert RESET, but do not assert TRST.
Output
Output Debug Event—DE provides a low pulse on recognized debug events.
Part 3 Specifications
3.1 General Characteristics
The 56F801 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The
term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology,
to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V- compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 14 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The 56F801 DC and AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
56F801 Technical Data
For More Information On This Product,
Go to: www.freescale.com
11
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| PDF Descargar | [ Datasheet F801FA60.PDF ] | |
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