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EM28C1604C3FL の電気的特性と機能

EM28C1604C3FLのメーカーはNanoAmp Solutionsです、この部品の機能は「Flash and SRAM Combo Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 EM28C1604C3FL
部品説明 Flash and SRAM Combo Memory
メーカ NanoAmp Solutions
ロゴ NanoAmp Solutions ロゴ 




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EM28C1604C3FL Datasheet, EM28C1604C3FL PDF,ピン配置, 機能
EM28C1604C3FL
NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
EM28C1604C3FL
Advance Information
Low Voltage, Extended Temperature
FLASH AND SRAM COMBO MEMORY
www.datasheet4u.com
FEATURES
• Organization: 1,048K x 16 (Flash)
256K x 16 (SRAM)
• Basic configuration:
Flash
Thirty-nine erase blocks
– Eight 4K-word parameter blocks
– Thirty-one 32K-word main memory blocks
SRAM
4Mb SRAM for data storage
– 256K-words
• F_VCC, VCCQ, F_VPP, S_VCC voltages
2.7V (MIN)/3.3V (MAX) F_VCC read voltage
2.7V (MIN)/3.3V (MAX) S_VCC read voltage
2.2V (MIN)/3.3V (MAX) VCCQ
1.8V (TYP) F_VPP (in-system PROGRAM/ERASE)
12V ±5% (HV) F_VPP (production programming
compatibility)
1.0V (MIN) S_VCC (SRAM data retention)
• Asynchronous access time
Flash access time: 85ns @ 3.0V F_VCC
Flash access time: 90ns @ 2.7V F_VCC
SRAM access time: 85ns @ 2.7V S_VCC
• Low power consumption
• Enhanced WRITE/ERASE suspend option
• Read/Write SRAM during program/erase of Flash
• 128-bit chip OTP protection register for security
purposes
• Cross-compatible command set support
• PROGRAM/ERASE cycles
100,000 WRITE/ERASE cycles per block
BALL ASSIGNMENT
66-Ball FBGA (Top View)
1 2 3 4 5 6 7 8 9 10 11 12
A NC NC NC A11 A15 A14 A13 A12 F_Vss F_VccQ NC NC
B A16 A8
A10 A9 DQ15 S_W E# DQ14 DQ7
C F_WE # NC
DQ13
DQ6 DQ4 DQ5
D S_Vss F_RP#
DQ12 S_CE2 S_Vcc F_Vcc
E F_WP # F_Vpp
A19 DQ11
DQ10
DQ2 DQ3
F S_LB# S_UB# S_OE #
DQ9 DQ8 DQ0 DQ1
G A18 A17 A7 A6 A3 A2 A1 S_CE1#
H NC NC NC A5 A4 A0 F_CE# F_Vss F_OE# NC NC NC
OPTIONS
• Timing
90ns
MARKING
-9
• Boot Block
Top
Bottom
T
B
• Operating Temperature Range
Extended Temperature (-40oC to +85oC)
ET
• Package
66-ball FBGA (8 x 8 grid)
FL
Part Number Example:
EM28C1604C3FL-9 TET
Stock No. 23133-A 1/01
1
Advance - Subject to Change without Notice

1 Page





EM28C1604C3FL pdf, ピン配列
NanoAmp Solutions, Inc.
www.datasheet4u.com
EM28C1604C3FL
Advance
RP#
CE#
WE#
OE#
A0-A19
DQ0-DQ15
Data Input
Buffer
CSM
FLASH FUNCTIONAL BLOCK DIAGRAM
Data
Register
X DEC
Y/Z DEC
Bank a Blocks
Y/Z Gating/Sensing
ID
Reg.
Status
Reg.
WSM
I/O Logic
Program/
Erase Change
Pump Voltage
Switch
Address
Input
Buffer
APS
Control
Address
CNT WSM
Address Latch
Address
Multiplexer
Output
Multiplexer
Data
Comparator
DQ0-DQ15
Output
Buffer
Y/Z DEC
X DEC
Y/Z Gating/Sensing
Bank b Blocks
Stock No. 23133-A 1/01
3
Advance - Subject to Change without Notice


3Pages


EM28C1604C3FL 電子部品, 半導体
NanoAmp Solutions, Inc.
EM28C1604C3FL
Advance
TRUTH TABLE – FLASH
MODES
FLASH SIGNALS
SRAM SIGNALS
MEMORY OUPUT
F_RP# F_CE# F_OE# F_WE#S_CE1#S_CE2 S_OE# S_WE# S_UB# S_LB# MEMORY
DQ0–DQ15
BUS CONTROL
Read
HL LH
wwwW.driatetasheet4u.comH L H L
Standby
HH XX
Output Disable H L H H
Reset
LXXX
SRAM must be High-Z
SRAM any mode allowable
Flash
Flash
Other
Other
Other
DOUT
DIN
High-Z
High-Z
High-Z
NOTES
1, 2, 3
1
4, 5
4, 6
4, 7
TRUTH TABLE – SRAM
MODES
Read
DQ0–DQ15
DQ0–DQ7
DQ8–DQ15
Write
DQ0–DQ15
DQ0–DQ7
DQ8–DQ15
Standby
Output Disable
Data Retention
FLASH SIGNALS
SRAM SIGNALS
MEMORY OUPUT
F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB# MEMORY DQ0–DQ15
BUSCONTROL
Flash must be High-Z
Flash any mode allowable
L
L
L
L
L
L
H
X
L
HLHL
HL HH
HLHL
HHL L
HHL H
HHL L
XXXX
LXXX
HHH X
Same as standby
L
L
H
L
L
H
X
X
X
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
Other
Other
Other
Other
DOUT
DOUT LB
DOUT UB
DIN
DIN LB
DIN UB
High-Z
High-Z
High-Z
High-Z
NOTES
1, 3
8
9
1, 3
10
11
4, 5
4, 5
4, 5
4, 6
NOTES: 1. Two devices may not drive the memory bus at the same time.
2. Allowable flash read modes include read array, read configuration, and read status.
3. Outputs are dependent on a separate device controlling bus outputs.
4. Modes of the Flash and SRAM can be interleaved so that while one is disabled, the other controls outputs.
5. The SRAM may be placed into data retention mode by lowering S_VCC to the VDR range, as specified.
6. SRAM is enabled and/or disabled with the logical function: S_CE1# or S_CE2.
7. Simultaneous operations can exist, as long as the operations are interleaved such that only one device attempts to
control the bus outputs at a time.
8. Data output on lower byte only; upper byte High-Z.
9. Data output on upper byte only; lower byte High-Z.
10. Data input on lower byte only.
11. Data input on upper byte only.
Stock No. 23133-A 1/01
6
Advance - Subject to Change without Notice

6 Page



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部品番号部品説明メーカ
EM28C1604C3FL

Flash and SRAM Combo Memory

NanoAmp Solutions
NanoAmp Solutions


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