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PDF ISL6611A Data sheet ( Hoja de datos )
| Número de pieza | ISL6611A | |
| Descripción | Phase Doubler | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
March 19, 2009
ISL6611A
FN6881.0
Phase Doubler with Integrated Drivers
and Phase Shedding Function
www.TdahteasIhSeLe6t46u1.1cAomutilizes Intersil’s proprietary Phase Doubler
scheme to modulate two-phase power trains with single
PWM input. It doubles the number of phases that Intersil’s
ISL63xx multiphase controllers can support. At the same
time, the PWM line can be pulled high to disable the
corresponding phase or higher phase(s) when the enable
pin (EN_PH) is pulled low. This simplifies the phase
shedding implementation. For layout simplicity and
improving system performance, the device integrates two 5V
drivers (ISL6609) and current balance function.
The ISL6611A is designed to minimize the number of analog
signals interfacing between the controller and drivers in high
phase count and scalable applications. The common COMP
signal, which is usually seen with conventional cascaded
configuration, is not required; this improves noise immunity
and simplifies the layout. Furthermore, the ISL6611A
provides low part count and a low cost advantage over the
conventional cascaded technique.
The IC is biased by a single low voltage supply (5V),
minimizing driver switching losses in high MOSFET gate
capacitance and high switching frequency applications.
Bootstrapping of the upper gate driver is implemented via an
internal low forward drop diode, reducing implementation
cost, complexity, and allowing the use of higher
performance, cost effective N-Channel MOSFETs. Adaptive
shoot-through protection is integrated to prevent both
MOSFETs from conducting simultaneously.
The ISL6611A features 4A typical sink current for the lower
gate driver, enhancing the lower MOSFET gate hold-down
capability during PHASE node rising edge, preventing power
loss caused by the self turn-on of the lower MOSFET due to
the high dV/dt of the switching node.
The ISL6611A also features an input that recognizes a
high-impedance state, working together with Intersil
multiphase PWM controllers to prevent negative transients
on the controlled output voltage when operation is
suspended. This feature eliminates the need for the Schottky
diode that may be utilized in a power system to protect the
load from negative output voltage damage.
In addition, the ISL6611A’s bootstrap function is designed to
prevent the BOOT capacitor from overcharging, should
excessively large negative swings occur at the transitions of
the PHASE node.
Features
• Proprietary Phase Doubler Scheme with Phase Shedding
Function (Patent Pending)
- Enhanced Light to Full Load Efficiency
• Patented Current Balancing with rDS(ON) Current Sensing
and Adjustable Gain
• Quad MOSFET Drives for Two Synchronous Rectified
Bridge with Single PWM Input
• Channel Synchronization and Interleaving Options
• Adaptive Zero Shoot-Through Protection
• 0.4Ω On-Resistance and 4A Sink Current Capability
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention (ISL6611A)
• Supports High Switching Frequency (Up to 1MHz)
- Fast Output Rise and Fall
• Tri-State PWM Input for Output Stage Shutdown
• Phase Enable Input and PWM Forced High Output to
Interface with Intersil’s Controller for Phase Shedding
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat
No Leads-Product Outline
- Near Chip-Scale Package Footprint; Improves PCB
Utilization, Thinner Profile
- Pb-Free (RoHS Compliant)
Applications
• High Current Low Voltage DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
• High Phase Count and Phase Shedding Applications
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6611A
Typical Application I (2-Phase Controller for 4-Phase Operation)
www.datasheet4u.com
+5V
FB
COMP
VR_RDY
VID
VSEN
VCC
PWM1
EN
MAIN
CONTROL
ISL63xx
+5V
+5V
SYNC
VCC AND PVCC BOOTA
EN_PH
SYNC
UGATEA
PHASEA
LGATEA
ISL6611A
PWM
BOOTB
IGAIN
UGATEB
PHASEB
LGATEB
GND AND PGND
+12V
+12V
ISEN1-
ISEN1+
FS
PWM2
EN_PH
+5V
VCC AND PVCC BOOTA
EN_PH
SYNC
UGATEA
PHASEA
ISL6611A
LGATEA
PWM
BOOTB
UGATEB
PHASEB
IGAIN
LGATEB
+12V
+12V
GND AND PGND
ISEN2-
ISEN2+
GND
+VCORE
5 FN6881.0
March 19, 2009
5 Page 
ISL6611A
PVCC
BOOT
RHI1
RLO1
UGATE
www.datasheet4u.com
PHASE
CGD
G
RG1
RGI1
CGS
S
D
CDS
Q1
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
RHI2 LGATE
RLO2
GND
CGD
G
RG2
RGI2
CGS
S
D
CDS
Q2
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
EN_PH Operation
EN_PH
PWM
UGATE
LGATE
FIGURE 5. TYPICAL EN_PH OPERATION TIMING DIAGRAM
The ISL6611A disables the phase doubler operation when the
EN_PH pin is pulled to ground and after it sees the PWM
falling edge. The PWM pin is pulled to VCC at the PWM falling
edge. With the PWM line pulled high, the controller will disable
the corresponding phase and the higher number phases.
When the EN_PH is pulled high, the phase doubler will pull
the PWM line to tri-state and then will be enabled at the
leading edge of PWM input. Prior to a leading edge of PWM, if
the PWM is low, both LGATEA and LGATEB remain in tri-
state unless the corresponding phase node (PHASEA,
PHASEB) is higher than 80% of VCC. This provides additional
protection if the doubler is enabled while the high-side
MOSFET is shorted. However, this feature limits the
pre-charged output voltage to less than 80% of VCC. Note
that the first doubler should always tie its EN_PH pin high
since Intersil controllers do not allow PWM1 pulled high and
this channel should remain ON to protect the system from an
overvoltage event even when the controller is disabled.
SYNC Operation
The ISL6611A can be set to interleaving mode or
synchronous mode by pulling the SYNC pin to GND or VCC,
respectively. A synchronous pulse can be sent to the phase
doubler during the load application to improve the voltage
droop and current balance while it still can maintain
interleaving operation at DC load conditions. However, an
excessive ringback can occur; hence, the synchronous
mode operation could have drawbacks. Figure 6 shows how
to generate a synchronous pulse only when an transient
load is applied. The comparator should be a fast comparator
with a minimum delay.
20kΩ
COMP
2kΩ
49.9kΩ
+
-
1.0 nF
VCC
0Ω
1kΩ
SYNC
DNP
FIGURE 6. TYPICAL SYNC PULSE GENERATOR
Current Balance and Maximum Frequency
The ISL6611A utilizes rDS(ON) sensing technique to balance
both channels, while the sample and hold circuits refer to
GND pin. The phase current sensing resistors are
integrated, while the current gain can be scaled by the
impedance on the IGAIN pin, as shown in Table 1. In most
applications, the default option should just work fine.
TABLE 1. CURRENT GAIN SELECTION
IMPEDANCE TO GND
CURRENT GAIN
OPEN
0Ω
DEFAULT
DEFAULT/2
49.9kΩ
DEFAULT/5
In addition to balancing the effective UGATE pulse width of
phase A and phase B via standard rDS(ON) current sensing
technique, a fast path is also added to swap both channels’
firing order when one phase carries much higher current
than the other phase. This improves the current balance
between phase A and phase B during high frequency load
transient events.
Each phase starts to sample current 200ns (tBLANK) after
LGATE falls and lasts for 400ns (tSAMP) or ends at the rising
edge of PWM if the available sampling time (tAVSAMP) is
< 400ns. The available sampling time (tAVSAMP) depends
upon the blanking time (tBLANK), the duty cycle (D), the
rising and falling time of low-side gate drive (tLR, tLF), the
total propagation delay (tPD = tPDLL + tPDLU), and the
switching frequency (FSW). As the switching frequency and
the duty cycle increase, the available sampling time could be
11 FN6881.0
March 19, 2009
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ISL6611A.PDF ] | |
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