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FOD8001のメーカーはFairchild Semiconductorです、この部品の機能は「3.3V Logic Gate Optocoupler」です。 |
部品番号 | FOD8001 |
| |
部品説明 | 3.3V Logic Gate Optocoupler | ||
メーカ | Fairchild Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとFOD8001ダウンロード(pdfファイル)リンクがあります。 Total 12 pages
March 2009
FOD8001
www.datasheet4u.com
High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Features
■ High Noise Immunity characterized by Common Mode
Rejection (CMR) and Power Supply Rejection (PSR)
specifications
– 20kV/µs Minimum Static CMR @ Vcm = 1000V
– 25kV/µs Typical Dynamic CMR @ Vcm = 1500V,
20MBaud Rate
– PSR in excess of 10% of the supply voltages
across full operating bandwidth
■ High Speed:
– 25Mbit/sec Date Rate (NRZ)
– 40ns max. Propagation Delay
– 6ns max. Pulse Width Distortion
– 20ns max. Propagation Delay Skew
■ 3.3V and 5V CMOS Compatibility
■ Extended industrial temperate range, -40°C to 105°C
temperature range
■ Safety and regulatory pending approvals:
– UL1577, 3750 VACRMS for 1 min.
– IEC60747-5-2 (pending)
Applications
■ Industrial fieldbus communications
– Profibus, DeviceNet, CAN, RS485
■ Programmable Logic Control
■ Isolated Data Acquisition System
Description
The FOD8001 is a 3.3V/5V high-speed logic gate
Optocoupler, which supports isolated communications
allowing digital signals to communicate between sys-
tems without conducting ground loops or hazardous
voltages. It utilizes Fairchild’s patented coplanar packag-
ing technology, Optoplanar®, and optimized IC design to
achieve high noise immunity, characterized by high
common mode rejection and power supply rejection
specifications.
This high-speed logic gate optocoupler, packaged in a
compact 8-pin small outline package, consists of a high-
speed AlGaAs LED driven by a CMOS buffer IC coupled
to a CMOS detector IC. The detector IC comprises an
integrated photodiode, a high-speed transimpedance
amplifier and a voltage comparator with an output driver.
The CMOS technology coupled to the high efficiency of
the LED achieves low power consumption as well as
very high speed (40ns propagation delay, 6ns pulse
width distortion).
Related Resources
■ www.fairchildsemi.com/products/opto/
■ www.fairchildsemi.com/pf/FO/FOD0721.html
■ www.fairchildsemi.com/pf/FO/FOD0720.html
■ www.fairchildsemi.com/pf/FO/FOD0710.html
Functional Schematic
VDD1 1
8 VDD2
VI 2
7 NC
* 3 6 VO
GND1 4
5 GND2
*: Pin 3 must be left unconnected
©2008 Fairchild Semiconductor Corporation
FOD8001 Rev. 1.0.2
Truth Table
VI LED
H OFF
L ON
VO
H
L
www.fairchildsemi.com
1 Page Isolation Characteristics (Apply over all recommended conditions, typical value is measured at TA = 25°C)
Symbol
Characteristics
Test Conditions
Min. Typ.* Max. Unit
VISO
RISO
www.datasheet4CuI.ScOom
Input-Output Isolation Voltage
Isolation Resistance
Isolation Capacitance
f = 60Hz, t = 1.0 min, II-O ≤ 10µA(5)(6)
VI-O = 500V(5)
VI-O = 0V, f = 1.0MHz(5)
3750
1011
—
—
—
0.2
— VacRMS
—Ω
— pF
Notes:
5. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted
together.
6. 3,750 VACRMS for 1 minute duration is equivalent to 4,500 VACRMS for 1 second duration.
Electrical Characteristics (Apply over all recommended conditions, typical value is measured at
VDD1 = VDD2 = +3.3V, VDD1 = +3.3V and VDD2 = +5.0V, VDD1 = +5.0V and VDD2 = +3.3V, VDD1 = VDD2 = +5.0V, TA = 25°C)
Symbol
Parameter
Conditions
Min. Typ. Max. Units
INPUT CHARACTERISTICS
IDD1L Logic Low Input Supply
Current
VI = 0V
6.2 10.0 mA
IDD1H Logic High Input Supply
Current
VI = VDD1
0.8 3.0
mA
IIA, IIB Input Current
OUTPUT CHARACTERISTICS
-10 +10 µA
IDD2L Logic Low Output Supply
Current
VI = 0V
4.5 9.0
mA
IDD2H Logic High Output Supply
Current
VI = VDD1
4.5 9.0
mA
VOH Logic High Output Voltage IO = -20µA, VI = VIH, VDD2 = +3.3V 2.9 3.3
IO = -4mA, VI = VIH, VDD2 = +3.3V
1.9 2.9
IO = -20µA, VI = VIH, VDD2 = +5.0V 4.4 5.0
IO = -4mA, VI = VIH, VDD2 = +5.0V
4.0 4.8
VOL Logic Low Output Voltage
IO = 20µA, VI = VIL
0 0.1
IO = 4mA, VI = VIL
0.3 1.0
V
V
©2008 Fairchild Semiconductor Corporation
FOD8001 Rev. 1.0.2
3
www.fairchildsemi.com
3Pages Typical Performance Curves (Continued)
Figure 7. Typical Propogation Delay vs. Output Load Capacitance
34
Frequency = 12.5MHz
Duty Cycle = 50%
VDD1 = VDD2 = 3.3V
32
www.datasheet4u.com
30
t
28 PHL
26 t
PL H
24
22
15 20 25 30 35 40 45 50 55
CL - Output Load Capacitance (pF)
Figure 8. Typical Width Distortion vs. Output Load Capacitance
2.6
Frequency = 12.5MHz
Duty Cycle = 50%
2.4 VDD1 = VDD2 = 3.3V
2.2
2.0
1.8
1.6
1.4
1.2
1.0
15 20 25 30 35 40 45 50 55
C L - Output Load Capacitance (pF)
Figure 9. Typical Rise Time vs. Output Load Capacitance
12
Frequency = 12.5MHz
Duty Cycle = 50%
11 VDD1 = VDD2 = 3.3V
10
9
8
7
6
5
4
15 20 25 30 35 40 45 50 55
CL - Output Load Capacitance (pF)
Figure 10. Typical Fall Time vs. Output Load Capacitance
16
Frequency = 12.5MHz
Duty Cycle = 50%
VDD1 = VDD2 = 3.3V
14
12
10
8
6
4
2
15 20 25 30 35 40 45 50 55
CL - Output Load Capacitance (pF)
Figure 11. Input Supply Current vs. Frequency
6.5
VDD1 = 5.5V
6.0
5.5
T = 105°C
A
5.0 T = 25°C
A
4.5
T = -40°C
A
4.0
3.5
3.0
0
2000
4000
6000
8000
f - Frequency (kHz)
10000 12000
Figure 12. Output Supply Current vs. Frequency
6.0
V DD1 = VDD2 = 5.5V
* Pin 6 Floating
5.8
T = 25°C
A
5.6
T = -40°C
A
5.4 T = 105°C
A
5.2
5.0
0
2000
4000
6000
8000
f - Frequency (kHz)
10000 12000
©2008 Fairchild Semiconductor Corporation
FOD8001 Rev. 1.0.2
6
www.fairchildsemi.com
6 Page | |||
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部品番号 | 部品説明 | メーカ |
FOD8001 | 3.3V Logic Gate Optocoupler | Fairchild Semiconductor |