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PDF STA333ML Data sheet ( Hoja de datos )
| Número de pieza | STA333ML | |
| Descripción | 2-channel microless high-efficiency digital audio system | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STA333ML
2-channel microless high-efficiency digital audio system
Sound Terminal ®
Datasheet − production data
Features
■ Wide supply voltage range (4.5 - 20 V)
■ 2 x 20 W into 8 Ω at VCC = 18 V
■ PowerSSO-36 exposed pad package
■ 2 channels of 24-bit DDX®
■ 100-dB SNR and dynamic range
■ Selectable 32 kHz to 48 kHz input sample
rates
■ Automatic zero-detect mute
■ Automatic invalid input detect mute
■ 2-channel I2S input data interface
■ Selectable clock input ratio (256 or 364 * fs)
■ Max power correction for lower full power
■ 96 kHz internal processing sample rate, 24-bit
precision
■ Embedded thermal overload and short-circuit
protection
■ Filterless configuration option
Applications
■ LCDs
■ DVDs
■ Cradles
■ Digital speakers
■ Wireless speaker cradles
PowerSSO-36
with exposed
pad down (EPD)
Description
The STA333ML is a single die embedding digital
audio processing and high-efficiency power
amplification, capable of operating without the aid
of an external microcontroller.
The STA333ML is part of the Sound Terminal®
family that provides full digital audio streaming to
the speakers and offers cost effectiveness, low
power dissipation and sound enrichment.
The STA333ML combines a unique 24-bit DDX®
digital class-D ternary modulator together with an
extremely low RdsON stereo power DMOS stage.
The latter is capable of a total output power of
2 x 20 W with outstanding performance in terms
of efficiency (>90%), THD, SNR and EMI.
The microless feature allows its use in low-cost
applications (cradles, digital speakers, audio
terminals) where no microcontroller is needed.
The serial audio data interface accepts the
universally used I2S format. Basic features, such
as the oversampling clock, gain, and I2S format,
can be set using a minimal number of selection
pins.
The STA333ML is self-protected against thermal
overload, overcurrent, short-circuit and
overvoltage conditions.
The fault condition is also signalled on an external
pin (INT_LINE) for specific requirements.
Table 1. Device summary
Order code
STA333ML
STA333ML13TR
Package
PowerSSO-36 EPD
PowerSSO-36 EPD
Packaging
Tube
Tape and reel
March 2012
This is information on a product in full production.
Doc ID 13177 Rev 6
1/21
www.st.com
21
1 page  
STA333ML
Pin description
Table 2.
Pin
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
-
Pin description (continued)
Name
Type
Description
VCC1
GND1
OUT1A
GND_REG
Power
Gnd
Out
Analog
Power positive supply
Power negative supply
Output half-bridge 1A
Internal ground reference
VDD_REG
CONFIG
N.C.
N.C.
Analog
In
-
-
Internal 3.3 V reference voltage
Configuration mode, must be connected to ground
Not connected
Not connected
N.C.
N.C.
VDD_DIG
GND_DIG
-
-
Power
Gnd
Not connected
Not connected
Positive supply digital
Digital ground
PWRDN
VDD_PLL
In
Power
Power-down:
0: low-power mode
1: normal operation
Positive supply for PLL
FILTER_PLL
GND_PLL
XTI
BICKI
LRCKI
SDI
RESET
INT_LINE
ONSEL
GAIN
GND_DIG
VDD_DIG
In
Gnd
In
In
In
In
In
Out
In
In
Gnd
Power
Connection to PLL filter
Negative supply for PLL
PLL input clock, 256 * fs or 384 * fs
I2S serial clock
I2S left/right clock
I2S serial data channel
Reset
Fault interrupt
Oversampling selector:
0: 256 * fs
1: 384 * fs
Gain selector:
0: 0 dBFs
1: 24 dBFs
Digital ground
Digital supply
EP
-
Exposed pad for PCB heatsink, to be connected to
ground plane
Doc ID 13177 Rev 6
5/21
5 Page 
STA333ML
Functional description
4.2 Fault-detect recovery bypass
The on-chip power output block provides feedback to the digital controller using inputs to
the power control block. The fault input is used to indicate a fault condition (either
overcurrent or thermal). When fault is asserted (set to 0), the power control block attempts a
recovery from the fault by asserting the 3-state output (setting it to 0 which directs the power
output block to begin recovery), holds it at 0 for 1 ms and then toggles it back to 1. This
sequence is repeated for as long as the fault exists.
4.3 Zero-detect mute enable
If this function is enabled, the zero-detect circuit examines each processing channel to see if
2048 consecutive zero value samples (regardless of fs) are received. If so, the channel is
muted.
4.4 Fade-in/out feature
The STA333ML has internal fade-in / fade-out feature when powered on or off, or after a
fault condition.
4.5 Oversampling selector
Pin ONSEL (33) is used to configure the PLL to accept 256 * fs or 384 * fs master clock.
Where fs is the I2S LRCKI frequency:
ONSEL = logical 0 gives 256 * fs
ONSEL = logical 1 gives 384 * fs.
4.6 Gain selector
Pin GAIN (34) is used to configure the STA333ML gain:
GAIN = logical 0 gives 0 dBFs
GAIN = logical 1 gives 24 dBFs.
4.7 Power-down function
Pin PWDN (23) is used to power down the STA333ML:
PWDN = logical 0 sets the power-down mode
PWDN = logical 1 gives normal operation.
If the power stage is switched off, then the PLL is also switched off.
It is possible to use the PWDN function as a mute function.
Doc ID 13177 Rev 6
11/21
11 Page | ||
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