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PDF ISL73096RH Data sheet ( Hoja de datos )

Número de pieza ISL73096RH
Descripción Radiation Hardened Ultra High Frequency NPN/PNP Transistor Arrays
Fabricantes Intersil Corporation　
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Radiation Hardened Ultra High Frequency NPN/PNP
Transistor Arrays
ISL73096RH, ISL73127RH, ISL73128RH, ISL73096EH, ISL73127EH,
ISL73128EH
The ISL73096, ISL73127 and ISL73128 are radiation
hardened bipolar transistor arrays. The ISL73096 consists of
three NPN transistors and two PNP transistors on a common
substrate. The ISL73127 consists of five NPN transistors on a
common substrate. The ISL73128 consists of five PNP
transistors on a common substrate.
The ISL73096EH, ISL73127EH and ISL73128EH devices
encompass all of the production testing of the ISL73096RH,
ISL73127RH and ISL73128RH devices and additionally are
tested in the Intersil Enhanced Low Dose Rate Sensitivity
(ELDERS) product manufacturing flow.
One of our bonded wafer, dielectrically isolated fabrication
processes provides an immunity to single event latch-up and
the capability of highly reliable performance in a radiation
environment.
The high gain-bandwidth product and low noise figure of these
transistors make them ideal for use in high frequency
amplifier and mixer applications. Monolithic construction of
the NPN and PNP transistors provides the closest electrical
and thermal matching possible. Access is provided to each
terminal of the transistors for maximum application flexibility.
Features
• Electrically screened to SMD # 5962-07218
• QML qualified per MIL-PRF-38535 requirements
• Radiation tolerance
- High dose rate (50-300rad(Si)/s). . . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . 50krad(Si)*
- SEL immune . . . . . . . . . . Bonded wafer dielectric isolation
• NPN gain bandwidth product (FT) . . . . . . . . . . . . . . 8GHz (typ)
• NPN current gain (hFE) . . . . . . . . . . . . . . . . . . . . . . . . 130 (typ)
• NPN early voltage (VA) . . . . . . . . . . . . . . . . . . . . . . . . . 50V (typ)
• PNP gain bandwidth product (FT). . . . . . . . . . . . . 5.5GHz (typ)
• PNP current gain (hFE). . . . . . . . . . . . . . . . . . . . . . . . . . 60 (typ)
• PNP early voltage (VA) . . . . . . . . . . . . . . . . . . . . . . . . . 20V (typ)
• Noise figure (50) at 1GHz. . . . . . . . . . . . . . . . . . . 3.5dB (typ)
• Collector-to-collector leakage . . . . . . . . . . . . . . . . . . <1pA (typ)
• Complete isolation between transistors
* Limit established by characterization.
Related Literature
Applications
• AN1503, Amplifier Design Using ISL73096RH,
ISL73127RH, ISL73128RH Transistor Arrays
• TID REPORT for the Radiation Hardened UHF NPN/PNP
transistor array
• High frequency amplifiers and mixers
• High frequency converters
• Synchronous detector
120
115
110
105
100
95
90
85
80 0
50 100 150 200 250 300
krad(Si)
FIGURE 1. NPN BETA OVER TOTAL IONIZING DOSE (TID) FOR LOW
DOSE RATE (LDR) TO 50krads(Si) AND HIGH DOSE RATE
(HDR) TO 300krads(Si)
75
70
65
60
55
50
45
40
0 50 100 150 200 250 300
krad(Si)
FIGURE 2. PNP BETA OVER TOTAL IONIZING DOSE (TID) FOR LOW
DOSE RATE (LDR) TO 50krads(Si) AND HIGH DOSE RATE
(HDR) TO 300krads(Si)
June 27, 2014
FN6475.4
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2007, 2009, 2012, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

1 page




ISL73096RH pdf
ISL73096RH, ISL73127RH, ISL73128RH, ISL73096EH, ISL73127EH, ISL73128EH
Absolute Maximum Ratings
Collector to Emitter Voltage (Open Base)
ISL73096, ISL73127 (NPN Characteristics) . . . . . . . . . . . . . . . . . . . . +8V
ISL73096, ISL73128 (PNP Characteristics) . . . . . . . . . . . . . . . . . . . . . -8V
Collector to Base Voltage (Open Emitter)
ISL73096, ISL73127 (NPN Characteristics) . . . . . . . . . . . . . . . . . . . +12V
ISL73096, ISL73128 (PNP Characteristics) . . . . . . . . . . . . . . . . . . . .-10V
Emitter to Base Voltage (Reverse Bias)
ISL73096, ISL73127 (NPN Characteristics) . . . . . . . . . . . . . . . . . . +5.5V
ISL73096, ISL73128 (PNP Characteristics) . . . . . . . . . . . . . . . . . . . -4.5V
Collector Current at 100% Duty Cycle, at TJ +175°C . . . . . . . . . . . .11.3mA
Power Dissipation (Pd), at TA +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W
Power Dissipation (Pd), at TA +125°C. . . . . . . . . . . . . . . . . . . . . . . . . 0.41W
Thermal Information
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
16 Ld FLATPACK Package( Notes 3, 4) . . .
120
28
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (TJMAX) . . . . . . . . . . . . . . . . . . . . .+175°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. For JC, the “case temp” location is the center of the package underside.
Electrical Specifications TA = +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to
+125°C; across a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 to 300 rad(Si)/s or over a total ionizing dose of 50krad(Si)
with exposure a low dose rate of <10mrad(Si)/s at +25°C.
SYMBOL
NPN PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN MAX
(Note 5) TYP (Note 5) UNITS
V(BR)CBO
V(BR)CEO
V(BR)CES
V(BR)EBO
VCE(SAT)
VBE
Collector to Base Breakdown Voltage
Collector to Emitter Breakdown Voltage
Collector to Emitter Breakdown Voltage
Emitter to Base Breakdown Voltage
Collector to Emitter Saturation Voltage
Base to Emitter Voltage
IC = 100µA, IE = 0
IC = 100µA, IB = 0
IC = 100µA, base shorted to emitter
IE = 10µA, IC = 0
IC = 10mA, IB = 1mA
IC = 10mA
12
8
10
5.5
0.5
0.95
1.05
V
V
V
V
V
V
V
hFE DC Forward Current Transfer Ratio IC = 10mA, VCE = 2V
80
40
VA Early Voltage
PNP PARAMETER
V(BR)CBO
Collector to Base Breakdown Voltage
V(BR)CEO
Collector to Emitter Breakdown Voltage
V(BR)CES
Collector to Emitter Breakdown Voltage
V(BR)EBO
Emitter to Base Breakdown Voltage
VCE(SAT)
Collector to Emitter Saturation Voltage
VBE Base to Emitter Voltage
IC = 1mA, VCE = 3.5V
IC = -100µA, IE = 0
IC = -100µA, IB = 0
IC = -100µA, base shorted to emitter
IE = -10µA, IC = 0
IC = -10mA, IB = -1mA
IC = -10mA
20
10
8
10
4.5
0.5
0.95
1.05
V
V
V
V
V
V
V
V
hFE DC Forward Current Transfer Ratio IC = -10mA, VCE = -2V
40
20
VA Early Voltage
IC = -1mA, VCE = -3.5V
10
NOTE:
5. Compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design.
V
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5
FN6475.4
June 27, 2014

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ISL73096RH arduino
ISL73096RH, ISL73127RH, ISL73128RH, ISL73096EH, ISL73127EH, ISL73128EH
Package Outline Drawing
K16.A
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 2, 1/10
0.015 (0.38) PIN NO. 1
0.008 (0.20) ID OPTIONAL 1
2
0.050 (1.27 BSC)
PIN NO. 1
ID AREA
0.440 (11.18)
MAX
0.005 (0.13)
MIN
4
0.022 (0.56)
0.015 (0.38)
TOP VIEW
0.115 (2.92)
0.045 (1.14)
0.045 (1.14)
0.026 (0.66) 6
-C-
SEATING AND
BASE PLANE
0.285 (7.24)
0.245 (6.22)
0.13 (3.30)
MIN
LEAD FINISH
SIDE VIEW
0.009 (0.23)
0.004 (0.10)
-D-
0.370 (9.40)
0.250 (6.35)
0.03 (0.76) MIN
-H-
0.006 (0.15) LEAD FINISH
0.004 (0.10)
BASE
METAL
0.009 (0.23)
0.004 (0.10)
0.019 (0.48)
0.015 (0.38)
0.0015 (0.04)
MAX
0.022 (0.56)
0.015 (0.38)
3
SECTION A-A
NOTES:
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
4. Measure dimension at all four corners.
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Controlling dimension: INCH.
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FN6475.4
June 27, 2014

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