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PDF ISL6443A Data sheet ( Hoja de datos )
| Número de pieza | ISL6443A | |
| Descripción | Step-Down PWM and Single Linear Controller | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
December 7, 2007
ISL6443A
FN6600.1
300kHz Dual, 180° Out-of-Phase, Step-Down
PWM and Single Linear Controller
www.TdahteasIhSeLe6t44u4.3coAmis a high-performance, triple-output controller
optimized for converting wall adapter, battery or network
intermediate bus DC input supplies into the system supply
voltages required for a wide variety of applications. Each
output is adjustable down to 0.8V. The two PWMs are
synchronized at 180° out of phase, thus reducing the RMS
input current and ripple voltage.
The ISL6443A incorporates several protection features. An
adjustable overcurrent protection circuit monitors the output
current by sensing the voltage drop across the lower
MOSFET. Hiccup mode overcurrent operation protects the
DC/DC components from damage during output
overload/short circuit conditions. Each PWM has an
independent logic-level shutdown input (SD1 and SD2).
A single PGOOD signal is issued when soft-start is complete
on both PWM controllers and their outputs are within 10% of
the set point and the linear regulator output is greater than
75% of its setpoint. Thermal shutdown circuitry turns off the
device if the junction temperature exceeds +150°C.
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
RANGE
(°C)
PKG.
PACKAGE DWG. #
ISL6443AIRZ* 6443A IRZ -40 to +85 28 Ld 5x5 QFN L28.5x5
(See Note)
(Pb-free)
ISL6443AIVZ* 6443A IVZ -40 to +85 28 Ld TSSOP M28.173
(See Note)
(Pb-free)
Add “-TK” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• Wide Input Supply Voltage Range
- Variable 5.6V to 24V
- Fixed 4.5V to 5.6V
• Three Independently Programmable Output Voltages
• Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . 300kHz
• Out of Phase PWM Controller Operation
- Reduces Required Input Capacitance and Power
Supply Induced Loads
• No External Current Sense Resistor
- Uses Lower MOSFET’s rDS(ON)
• Bidirectional Frequency Synchronization for
Synchronizing Multiple ISL6443As
• Programmable Soft-Start
• Extensive Circuit Protection Functions
- PGOOD
- UVLO
- Overcurrent
- Over-temperature
- Independent Shutdown for Both PWMs
• Excellent Dynamic Response
- Voltage Feed-Forward with Current Mode Control
• QFN Packages:
- QFN - Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package Footprint, which Improves
PCB Efficiency and has a Thinner Profile
• Pb-Free (RoHS Compliant)
Applications
• Power Supplies with Multiple Outputs
• xDSL Modems/Routers
• DSP, ASIC, and FPGA Power Supplies
• Set-Top Boxes
• Dual Output Supplies for DSP, Memory, Logic, µP Core
and I/O
• Telecom Systems
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6443A
Absolute Maximum Ratings
Supply Voltage (VCC_5V Pin) . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Input Voltage (VIN Pin). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+27V
BOOT1, 2 and UGATE1, 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .+35V
PHASE1, 2 and ISEN1, 2
. . . . . . . . . . . . . . . . . . . . .-5V (<100ns, 10µJ)/-0.3V (DC) to +27V
BOOT1, 2 with Respect to PHASE1, 2 . . . . . . . . . . . . . . . . . . +6.5V
www.UEdaSGtDaAsTRhEea1tei,nt42gu. ..c.o.m. . . . . . . .(PHASE1, 2 - 0.3V) to (BOOT1, 2 + 0.3V)
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2000V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
28 Lead QFN (Notes 1, 2) . . . . . . . .
36
4
28 Lead TSSOP (Note 1) . . . . . . . . .
75
NA
Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θJC is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. For θJA
the “case temp” location is the center of the exposed metal pad on the underside of the package. See Tech Brief TB379.
2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 3 and “Typical
Application Schematic” on page 4. VIN = 5.6V to 24V, or VCC_5V = 5V ±10%, TA = -40°C to +85°C (Note 6),
Typical values are at TA = +25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VIN SUPPLY
Input Voltage Range
5.6 12
24
V
Input Voltage Range
VCC_5V SUPPLY (Note 3)
VIN = VCC (Note 3)
4.5 5.0 5.6
V
Input Voltage
4.5 5.0 5.6
V
Output Voltage
Maximum Output Current
SUPPLY CURRENT
VIN > 5.6V, IL = 20mA
VIN = 12V
4.5 5.0 5.5
V
60 -
- mA
Shutdown Current (Note 4)
SD1 = SD2 = GND
- 50 375 μA
Operating Current (Note 5)
- 2.0 4.0 mA
REFERENCE SECTION
Nominal Reference Voltage
- 0.8 -
V
Reference Voltage Tolerance
-1.0 - 1.0 %
POWER-ON RESET
Rising VCC_5V Threshold
4.25 4.45
4.5
V
Falling VCC_5V Threshold
3.95 4.2
4.4
V
OSCILLATOR
Total Frequency Variation
260 300 340 kHz
Peak-to-Peak Sawtooth Amplitude (Note 6)
Ramp Offset (Note 6)
VIN = 12V
VIN = 5V
- 1.6 -
- 0.667 -
- 1.0 -
V
V
V
SYNC Input Rise/Fall Time (Note 6)
- 5.0 - ns
SYNC Frequency Range
4.16 4.8 5.44 MHz
SYNC Input HIGH Level
3.5 - - V
SYNC Input LOW Level
- - 1.5 V
5 FN6600.1
December 7, 2007
5 Page 
ISL6443A
Functional Description
General Description
The ISL6443A integrates control circuits for two synchronous
buck converters and one linear controller. The two synchronous
bucks operate out-of-phase to substantially reduce the input
ripple and thus reduce the input filter requirements. The chip
www.hdatsasfohuerect4oun.tcrooml lines (SS1, SD1, SS2, and SD2), which provide
independent control for each of the synchronous buck outputs.
The buck PWM controllers employ a free-running frequency
of 300kHz. The current mode control scheme with an input
voltage feed-forward ramp input to the modulator provides
excellent rejection of input voltage variations and provides
simplified loop compensations.
The linear controller can drive either a PNP or PFET to provide
ultra low-dropout regulation with programmable voltages.
Internal 5V Linear Regulator (VCC_5V)
All ISL6443A functions are internally powered from an
on-chip, low dropout 5V regulator. The maximum regulator
input voltage is 24V. Bypass the regulator’s output
(VCC_5V) with a 4.7µF capacitor to ground. The dropout
voltage for this LDO is typically 600mV, so when VIN is
greater than 5.6V, VCC_5V is typically 5V. The ISL6443A
also employs an undervoltage lockout circuit that disables
both regulators when VCC_5V falls below 4.4V.
The internal LDO can source over 60mA to supply the IC,
power the low side gate drivers and charge the external boot
capacitor. When driving large FETs (especially at 300kHz
frequency), little or no regulator current may be available for
external loads.
For example, a single large FET with 15nC total gate charge
requires 15nC x 300kHz = 4.5mA. Also, at higher input
voltages with larger FETs, the power dissipation across the
internal 5V will increase. Excessive dissipation across this
regulator must be avoided to prevent the junction temperature
from rising. Larger FETs can be used with 5V ±10% input
applications. The thermal overload protection circuit will be
triggered if the VCC_5V output is short circuited. Connect
VCC_5V to VIN for 5V ±10% input applications.
Soft-Start Operation
When soft-start is initiated, the voltage on the SS pin of the
enabled PWM channels starts to ramp gradually, due to the
5μA current sourced into the external capacitor. The output
voltage follows the soft-start voltage.
When the SS pin voltage reaches 0.8V, the output voltage of
the enabled PWM channel reaches the regulation point, and
the soft-start pin voltage continues to rise. At this point the
PGOOD and fault circuitry is enabled. This completes the
soft-start sequence. Any further rise of SS pin voltage does
not affect the output voltage. By varying the values of the
soft-start capacitors, it is possible to provide sequencing of the
main outputs at start-up. The soft-start time can be obtained
from Equation 1:
tSOFT = 0.8V⎝⎛ -C5---μ-S---A-S--⎠⎞
(EQ. 1)
VCC_5V 1V/DIV
VOUT1 1V/DIV
SS1 1V/DIV
FIGURE 13. SOFT-START OPERATION
The soft-start capacitors can be chosen to provide start-up
tracking for the two PWM outputs. This can be achieved by
choosing the soft-start capacitors such that the soft-start
capacitor ratio equals the respective PWM output voltage
ratio. For example, if one uses PWM1 = 1.2V and PWM2 =
3.3V, then the soft-start capacitor ratio should be,
CSS1/CSS2 = 1.2/3.3 = 0.364. Figure 14 shows that soft-start
waveform with CSS1 = 0.01µF and CSS2 = 0.027µF.
VOUT2 1V/DIV
VOUT1 1V/DIV
FIGURE 14. PWM1 AND PWM2 OUTPUT TRACKING DURING
START-UP
Output Voltage Programming
A resistive divider from the output to ground sets the output
voltage of either PWM channel. The center point of the
divider shall be connected to FBx pin. The output voltage
value is determined by Equation 2.
VOUTx
=
0.8
V
⎛
⎜
⎝
R-----1--R---+--2--R-----2-⎠⎟⎞
(EQ. 2)
where R1 is the top resistor of the feedback divider network
and R2 is the resistor connected from FBx to ground.
11 FN6600.1
December 7, 2007
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ISL6443A.PDF ] | |
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