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Número de pieza | IXF18104 | |
Descripción | 10 Gigabit Lan PHY | |
Fabricantes | Intel Corporation | |
Logotipo | ||
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Intel® IXF18104
10 Gigabit LAN PHY
product brief
Product Overview
The Intel® IXF18104 is a highly integrated
solution for 10GbE Local Area Network (LAN)
port applications compliant as per IEEE802.3ae
specifications. The IXF18104 supports the
10GbE LAN mode of operation for transport
of Ethernet frames in LAN (10.3125Gbps)
applications.
The 10 Gigabit MAC (per IEEE 802.3ae)
handles frame encapsulation, verification,
10GbE flow control, and Remote Monitoring/
Simple Network Management Protocol
(RMON/ SNMP) statistics management. The
IXF18104 also handles the 802.3ae Physical
Coding Sub-layer (PCS) functions of the 10
Gigabit Ethernet standard. The PCS hardware
handles the 64B/66B encoding/decoding to
provide the transition density and balance
of the 10.3125Gbps stream.
The system interface supports the industry-
standard System Parallel Interface Level 4
(SPI-4) Phase 2. This interface is 16 bits wide
with 622Mbps–800Mbps Double Data Rate
(DDR) clocking. The SPI-4 Phase 2 interface
is Low Voltage Differential Signaling (LVDS),
which provides the customer with less
connection concerns than previous 64-bit
High-Speed Transport Layer (HSTL) interfaces.
On the line side, the IXF18104 supports
the LAN version of the IEEE 802.3ae XSBI
interface. The 16-bit LVDS interface operates
at 644Mbps to support the 10GbE LAN rate
of 10.3125Gbps.
The IXF18104 also supports an integrated
Pseudo Random Bit Sequence (PRBS) packet
generator/analyzer for the PCS. Line remote,
line local, system remote, and system local
loop backs are supported for general devel-
opment functionality test and debug.
Intel® IXF18104 Block Diagram
16-bit LVDS
644Mbps
16
16
IEEE 802.3ae
XSBI Line
Interface
PCS 10 Gigabit
MAC
SPI-4
Phase 2
System
Interface
16
16
16-bit LVDS
622Mbps
800Mbps
DDR
Generic
µP Interface
16
1 page |
Páginas | Total 4 Páginas | |
PDF Descargar | [ Datasheet IXF18104.PDF ] |
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