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IS41C85120 の電気的特性と機能

IS41C85120のメーカーはIntegrated Silicon Solutionです、この部品の機能は「512K x 8 (4-MBIT) DYNAMIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS41C85120
部品説明 512K x 8 (4-MBIT) DYNAMIC RAM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS41C85120 Datasheet, IS41C85120 PDF,ピン配置, 機能
IS41C85120
IS41LV85120
512K x 8 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
ISSI®
PRELIMINARY INFORMATION
SEPTEMBER 2001
www.daFtaEshAeeTt4Uu.RcoEmS
• TTL compatible inputs and outputs
• Refresh Interval: 1024 cycles/16 ms
• Refresh Mode : RAS-Only, CAS-before-RAS
(CBR), and Hidden
• JEDEC standard pinout
• Single power supply
5V ± 10% (IS41C85120)
3.3V ± 10% (IS41LV85120)
• Industrail Temperature Range -40oC to 85oC
KEY TIMING PARAMETERS
Parameter
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. Fast Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)
-35
35
10
18
12
60
-60 Unit
60 ns
15 ns
30 ns
25 ns
110 ns
PIN DESCRIPTIONS
A0-A9
I/O0-I/O7
WE
OE
RAS
CAS
VCC
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
DESCRIPTION
The ISSI IS41C85120 and IS41LV85120 are 524,288 x 8-bit
high-performance CMOS Dynamic Random Access
Memory. Both products offer accelerated cycle access EDO
Page Mode. EDO Page Mode allows 512 random accesses
within a single row with access cycle time as short as 10ns per
8-bit word. The Byte Write control, of upper and lower byte,
makes the IS41C85120 and IS41LV85120 ideal for use in 16
and 32-bit wide data bus systems.
These features make the IS41C85120 and IS41LV85120
ideally suited for high band-width graphics, digital signal
processing, high-performance computing systems, and pe-
ripheral applications.
The IS41C85120 and IS41LV85120 are available in a
28-pin, 400-mil SOJ package.
PIN CONFIGURATION
28-Pin SOJ
VCC
I/O0
I/O1
I/O2
I/O3
NC
WE
RAS
A9
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 GND
27 I/O7
26 I/O6
25 I/O5
24 I/O4
23 CAS
22 OE
21 NC
20 A8
19 A7
18 A6
17 A5
16 A4
15 GND
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
09/25/01
1

1 Page





IS41C85120 pdf, ピン配列
IS41C85120
IS41LV85120
ISSI ®
TRUTH TABLE
Function
Standby
www.dataRsehaeedt:4uW.coomrd
Read: Lower Byte
RAS
H
L
L
CAS
H
L
L
WE
X
H
H
OE Address tR/tC
XX
L ROW/COL
L ROW/COL
Read: Upper Byte
L H H L ROW/COL
Write: Word (Early Write)
L L L X ROW/COL
Write: Lower Byte (Early Write)
L
L
L
X ROW/COL
Write: Upper Byte (Early Write)
L
H
L
X ROW/COL
Read-Write(1,2)
L L HL LH ROW/COL
EDO Page-Mode Read(2)
DOUT
1st Cycle:
2nd Cycle:
Any Cycle:
L
L
L
HL
HL
LH
H
H
H
L
L
L
EDO Page-Mode Write(1)
1st Cycle:
2nd Cycle:
L
L
HL
HL
L
L
X
X
EDO Page-Mode
DOUT, DIN
Read-Write(1,2)
1st Cycle:
2nd Cycle:
L
L
HL
HL
HL
HL
LH
LH
Hidden Refresh2)
DOUT
DOUT
Read LHL
L
H
L
Write LHL
L
L
X
RAS-Only Refresh
L H X X ROW/NA
CBR Refresh(3)
HL
L
X
X
X
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. At least one of the two CAS signals must be active (LCAS or UCAS).
I/O
High-Z
DOUT
Lower Byte, DOUT
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, DOUT
DIN
Lower Byte, DIN
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, DIN
DOUT, DIN
ROW/COL
NA/COL DOUT
NA/NA DOUT
ROW/COL
NA/COL DIN
ROW/COL
DIN
NA/COL DOUT, DIN
ROW/COL
ROW/COL
High-Z
High-Z
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
09/25/01
3


3Pages


IS41C85120 電子部品, 半導体
IS41C85120
IS41LV85120
ISSI ®
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max. Unit
www.IdIaLtasheet4u.Icnopmut Leakage Current
Any input 0V VIN Vcc
Other inputs not under test = 0V
10 10 µA
IIO Output Leakage Current
Output is disabled (Hi-Z)
0V VOUT Vcc
10 10 µA
VOH Output High Voltage Level
IOH = 2.5 mA
2.4
V
VOL Output Low Voltage Level
ICC1 Stand-by Current: TTL
IOL = +2.1 mA
RAS, CAS VIH
0.4 V
Commercial
Industrial
Commercial
Industrial
5V
5V
3V
3V
3 mA
4
2
3
ICC2 Stand-by Current: CMOS
RAS, CAS VCC 0.2V
5V
3V
2 mA
1
ICC3 Operating Current:
RAS, CAS,
Random Read/Write(2,3,4)
Address Cycling, tRC = tRC (min.)
Average Power Supply Current
ICC4 Operating Current:
RAS = VIL, CAS,
EDO Page Mode(2,3,4)
Cycling tPC = tPC (min.)
Average Power Supply Current
ICC5
Refresh Current:
RAS-Only(2,3)
RAS Cycling, CAS VIH
tRC = tRC (min.)
Average Power Supply Current
-35 230 mA
-60 170
-35 220 mA
-60 160
-35 230 mA
-60 170
ICC6 Refresh Current:
RAS, CAS Cycling
CBR(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
-35 230 mA
-60 170
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
09/25/01

6 Page



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共有リンク

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