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PDF IS41C8512 Data sheet ( Hoja de datos )
| Número de pieza | IS41C8512 | |
| Descripción | 512K x 8 (4-MBIT) DYNAMIC RAM | |
| Fabricantes | Integrated Circuit Solution | |
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IS41C8512
IS41LV8512
512K x 8 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
.EATURES
Extended Data-Out (EDO) Page Mode access cycle
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TTL compatible inputs and outputs; tristate I/O
Refresh Interval: 1024 cycles /16 ms
Refresh Mode: RAS-Only, CAS-before-RAS (CBR),
Hidden
JEDEC standard pinout
Single power supply:
5V ± 10% (IS41C8512)
3.3V ± 10% (IS41LV8512)
Byte Write and Byte Read operation via CAS
Industrail Temperature Range -40oC to 85oC
DESCRIPTION
The 1+51 IS41C8512 and IS41LV8512 is a 524,288 x 8-bit
high-performance CMOS Dynamic Random Access Memories.
The IS41C8512 offer an accelerated cycle access called EDO
Page Mode. EDO Page Mode allows 512 random accesses
within a single row with access cycle time as short as 10 ns per
8-bit.
These features make the IS41C8512and IS41LV8512 ideally
suited for high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
The IS41C8512 is packaged in a 28-pin 400mil SOJ and
400mil TSOP-2.
KEY TIMING PARAMETERS
Parameter
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. EDO Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)
-35 -50 -60 Unit
35 50 60 ns
10 14 15 ns
18 25 30 ns
12 20 25 ns
60 90 110 ns
PIN CON.IGURATIONS
28 Pin SOJ, TSOP-2
VCC
I/O0
I/O1
I/O2
I/O3
NC
WE
RAS
A9
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 GND
27 I/O7
26 I/O6
25 I/O5
24 I/O4
23 CAS
22 OE
21 NC
20 A8
19 A7
18 A6
17 A5
16 A4
15 GND
PIN DESCRIPTIONS
A0-A9
I/O0-7
WE
OE
RAS
CAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR008-0B
1
1 page  
IS41C8512
IS41LV8512
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min.
IIL Input Leakage Current
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IIO Output Leakage Current
Any input 0V < VIN < Vcc
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V < VOUT < Vcc
10
10
VOH Output High Voltage Level
IOH = 2.5 mA
2.4
VOL Output Low Voltage Level
IOL =+2.1mA
ICC1 Standby Current: TTL
RAS, CAS > VIH
Commerical
Industrial
Commerical
Industrial
5V
5V
3V
3V
ICC2 Standby Current: CMOS
RAS, CAS > VCC 0.2V
5V
3V
ICC3 Operating Current:
RAS, CAS,
Random Read/Write(2,3,4)
Address Cycling, tRC = tRC (min.)
Average Power Supply Current
-35
-50
-60
ICC4 Operating Current:
RAS = VIL, CAS,
EDO Page Mode(2,3,4)
Cycling tPC = tPC (min.)
Average Power Supply Current
-35
-50
-60
ICC5 Refresh Current:
RAS Cycling, CAS > VIH
RAS-Only(2,3)
tRC = tRC (min.)
Average Power Supply Current
-35
-50
-60
ICC6 Refresh Current:
RAS, CAS Cycling
CBR(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
-35
-50
-60
Max.
10
10
0.4
3
4
2
3
2
1
230
180
170
220
170
160
230
180
170
230
180
170
Unit
µA
µA
V
V
mA
mA
mA
mA
mA
mA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tRE. refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
DR008-0B
5
5 Page 
IS41C8512
IS41LV8512
READ WRITE CYCLE (LATE WRITE and READ-MODI.Y-WRITE Cycles)
www.datasheet4u.com
RAS
tCRP
CAS
tASR
ADDRESS
WE
I/O
OE
Row
tRWC
tRAS
tRP
tRCD
tCSH
tRSH
tCAS tCLCH
tRAD
tRAH
tAR
tASC
tCAH
tRAL
tACH
tRCS
Column
tRWD
tCWD
tAWD
Row
tCWL
tRWL
tWP
Open
tRAC
tCAC
tCLZ
tAA
tOE
tDS tDH
Valid DOUT Valid DIN
Open
tOD tOEH
Undefined
Don’t Care
Integrated Circuit Solution Inc.
DR008-0B
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet IS41C8512.PDF ] | |
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