|
|
PDF HD6417145 Data sheet ( Hoja de datos )
| Número de pieza | HD6417145 | |
| Descripción | (HD6437144 / HD6437145) 32-Bit RISC Microcomputer | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HD6417145 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
REJ09B0108-0400
www.datasheet4u.com
The revision list can be viewed directly by clicking the title page.
The revision list summarizes the locations of revisions and
additions. Details should always be checked by referring to the
relevant text.
32
SH7144 Group, SH7145 Group
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperHTM RISC engine Family/SH7144 Series
SH7114
SH7145
HD64F7144
HD6437144
HD6417144
HD64F7145
HD6437145
HD6417145
Rev.4.00
Revision Date: Mar. 27, 2008
1 page  
www.datasheet4u.com
Preface
The SH7144 Group and SH7145 Group single-chip RISC (Reduced Instruction Set Computer)
microcomputers integrate a Renesas Technology Corp. original RISC CPU core with peripheral
functions required for system configuration.
Target users: This manual was written for users who will be using this LSI in the design of
application systems. Users of this manual are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of this LSI to the above users.
Refer to the SH-1/SH-2/SH-DSP Software Manual for a detailed description of the
instruction set.
Notes on reading this manual:
• Product names
The following products are covered in this manual.
Product Classifications and Abbreviations
Basic Classification
On-Chip ROM Classification
SH7144 (112-pin version) SH7144F
Flash memory version
(ROM: 256 kbytes)
SH7144M
Masked ROM version
(ROM: 256 kbytes)
ROM less version
SH7145 (144-pin version) SH7145F
Flash memory version
(ROM: 256 kbytes)
SH7145M
Masked ROM version
(ROM: 256 kbytes)
ROM less version
Part No.
HD64F7144
HD6437144
HD6417144
HD64F7145
HD6437145
HD6417145
Rev.4.00 Mar. 27, 2008, Page v of xliv
REJ09B0108-0400
5 Page 
Section 6 Interrupt Controller (INTC) .............................................................. 77
w6w.1w.datFaesahteuerte4su.c..o..m........................................................................................................................ 77
6.2 Input/Output Pins ..............................................................................................................79
6.3 Register Descriptions ........................................................................................................79
6.3.1 Interrupt Control Register 1 (ICR1).....................................................................80
6.3.2 Interrupt Control Register 2 (ICR2).....................................................................82
6.3.3 IRQ Status Register (ISR)....................................................................................84
6.3.4 Interrupt Priority Registers A to J (IPRA to IPRJ)...............................................85
6.4 Interrupt Sources ...............................................................................................................87
6.4.1 External Interrupts ...............................................................................................87
6.4.2 On-Chip Peripheral Module Interrupts ................................................................88
6.4.3 User Break Interrupt ............................................................................................88
6.4.4 H-UDI Interrupt ...................................................................................................89
6.5 Interrupt Exception Processing Vectors Table ..................................................................90
6.6 Operation...........................................................................................................................93
6.6.1 Interrupt Sequence ...............................................................................................93
6.6.2 Stack after Interrupt Exception Processing ..........................................................95
6.7 Interrupt Response Time ...................................................................................................96
6.8 Data Transfer with Interrupt Request Signals ...................................................................98
6.8.1 Handling Interrupt Request Signals as Sources for DTC Activating and
CPU Interrupt, but Not DMAC Activating ..........................................................99
6.8.2 Handling Interrupt Request Signals as Sources for Activating DMAC,
but Not CPU Interrupt and DTC Activating ........................................................99
6.8.3 Handling Interrupt Request Signals as Source for DTC Activating,
but Not CPU Interrupt and DMAC Activating ....................................................99
6.8.4 Handling Interrupt Request Signals as Source for CPU Interrupt
but Not DMAC and DTC Activating ...................................................................100
Section 7 User Break Controller (UBC) ........................................................... 101
7.1 Features .............................................................................................................................101
7.2 Register Descriptions ........................................................................................................103
7.2.1 User Break Address Register (UBAR) ................................................................103
7.2.2 User Break Address Mask Register (UBAMR) ...................................................103
7.2.3 User Break Bus Cycle Register (UBBR) .............................................................104
7.2.4 User Break Control Register (UBCR)..................................................................105
7.3 Operation...........................................................................................................................106
7.3.1 Flow of User Break Operation .............................................................................106
7.3.2 Break on On-Chip Memory Instruction Fetch Cycle ...........................................108
7.3.3 Program Counter (PC) Values Saved...................................................................108
7.4 Examples of Use ...............................................................................................................109
Rev.4.00 Mar. 27, 2008, Page xi of xliv
REJ09B0108-0400
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD6417145.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HD6417144 | (HD6437144 / HD6437145) 32-Bit RISC Microcomputer | Renesas Technology |
| HD6417145 | (HD6437144 / HD6437145) 32-Bit RISC Microcomputer | Renesas Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |