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PDF HD6437065A Data sheet ( Hoja de datos )
| Número de pieza | HD6437065A | |
| Descripción | 32-Bit RISC Microcomputer | |
| Fabricantes | Renesas Technology | |
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REJ09B0332-0500
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The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
32
SH7065
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperH RISC engine Family/SH7000 Series
SH7065
HD6437065A
HD64F7065SF
HD64F7065AF
Rev. 5.00
Revision Date: Sep 11, 2006
1 page  
Preface
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The SH7065 is a microprocessor that integrates peripheral functions necessary for system
configuration with a 32-bit internal architecture SH2-DSP CPU as its core.
On-chip peripheral functions include large-capacity ROM and RAM, an interrupt controller, four
kinds of timers, a serial communication interface, user break controller (UBC), bus state controller
(BSC), direct memory access controller (DMAC), A/D converter, D/A converter, and I/O ports,
enabling the SH7065 to be used as a microcontroller for electronic products requiring high speed
and low power consumption. Flash memory (F-ZTAT™*) and mask ROM are available as on-
chip ROM, enabling users to respond quickly and flexibly to changing application specifications
and the demands of the transition from initial to full-fledged volume production.
Note: * F-ZTAT is a trademark of Renesas Technology Corp.
Intended Readership: This manual is intended for users undertaking the design of an application
system using the SH7065. Readers using this manual require a basic
knowledge of electrical circuits, logic circuits, and microcomputers.
Purpose:
The purpose of this manual is to give users an understanding of the hardware
functions and electrical characteristics of the SH7065. Details of execution
instructions can be found in the SH-1, SH-2, SH-DSP Programming Manual,
which should be read in conjunction with the present manual.
Using this Manual:
• For an overall understanding of the SH7065’s functions
Follow the Table of Contents. This manual is broadly divided into sections on the CPU, system
control functions, peripheral functions, and electrical characteristics.
• For a detailed understanding of CPU functions
Refer to the separate publication SH-1, SH-2, SH-DSP Programming Manual.
Note on bit notation: Bits are shown in high-to-low order from left to right.
Related Material: The latest information is available at our Web Site. Please make sure that you
have the most up-to-date information available.
http://www.renesas.com/
Rev. 5.00 Sep 11, 2006 page v of xxii
5 Page 
4.14 Module Clock Division Function ...................................................................................... 157
4.14.1 Clock Definitions ................................................................................................. 157
www.dat4a.s1h4e.e2t4uT.croamnsition to Module Clock Division Function.................................................... 158
4.14.3 Exit from Module Clock Division Function......................................................... 160
4.14.4 Notes on Use of Module Clock Division Function .............................................. 160
4.15 Note on Initialization......................................................................................................... 161
Section 5 Exception Handling ......................................................................................... 163
5.1 Overview........................................................................................................................... 163
5.1.1 Exception Handling Types and Priority ............................................................... 163
5.1.2 Timing of Exception Source Detection and Start of Exception Handling............ 164
5.1.3 Exception Vector Table ....................................................................................... 164
5.2 Power-on Reset ................................................................................................................. 167
5.3 Address Errors .................................................................................................................. 168
5.3.1 Address Error Sources ......................................................................................... 168
5.3.2 Address Error Exception Handling ...................................................................... 169
5.4 Interrupts ........................................................................................................................... 169
5.4.1 Interrupt Sources.................................................................................................. 169
5.4.2 Interrupt Priority .................................................................................................. 170
5.4.3 Interrupt Exception Handling............................................................................... 170
5.5 Instruction Exceptions....................................................................................................... 171
5.5.1 Types of Instruction Exception ............................................................................ 171
5.5.2 Trap Instruction.................................................................................................... 171
5.5.3 Slot Illegal Instructions ........................................................................................ 172
5.5.4 General Illegal Instructions .................................................................................. 172
5.6 Cases in Which Exceptions Are Not Accepted ................................................................. 173
5.6.1 After a Delayed Branch Instruction...................................................................... 173
5.6.2 After an Instruction for Which Interruption Is Prohibited.................................... 173
5.6.3 Instructions in Repeat Loops................................................................................ 174
5.7 Stack Status after Exception Handling .............................................................................. 175
5.8 Usage Notes ...................................................................................................................... 176
5.8.1 Stack Pointer (SP) Value...................................................................................... 176
5.8.2 Vector Base Register (VBR) Value ..................................................................... 176
5.8.3 Address Errors Occurring in Address Error Exception Handling Stacking ......... 176
Section 6 Interrupt Controller (INTC) ........................................................................... 177
6.1 Overview........................................................................................................................... 177
6.1.1 Features................................................................................................................ 177
6.1.2 Block Diagram ..................................................................................................... 178
6.1.3 Pin Configuration................................................................................................. 179
6.1.4 Register Configuration ......................................................................................... 179
Rev. 5.00 Sep 11, 2006 page xi of xxii
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