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PDF HD64F7055S Data sheet ( Hoja de datos )
| Número de pieza | HD64F7055S | |
| Descripción | 32-Bit RISC Microcomputer | |
| Fabricantes | Renesas Technology | |
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32
SH-2E SH7055S F-ZTATTM
Hardware Manual
Renesas 32-bit RISC Microcomputer
SuperHTM RISC engine Family/SH7000 Series
The revision list can be viewed directly by
clicking the title page.The revision list
summarizes the locations of revisions and
additions. Details should always be checked
by referring to the relevant text.
Rev. 2.00
2003.7.17
www.renesas.com
1 page  
Preface
wTwhwe.dSaHta7s0h5ee5tS4Fu.cisoma single-chip RISC (reduced instruction set computer) microcomputer that has
an original 32-bit RISC type CPU as its core, and also includes peripheral functions necessary for
system configuration.
The SH7055SF is equipped with on-chip peripheral functions necessary for system configuration,
including a floating-point unit (FPU), large-capacity ROM and RAM, a direct memory access
controller (DMAC), timers, a serial communication interface (SCI), Controller area network
(HCAN), A/D converter, interrupt controller (INTC), and I/O ports, therefore, it can be used as a
microprocessor built in a high-level control system.
The SH7055SF is an F-ZTAT™* (Flexible Zero Turn-Around Time) version with flash memory
as its on-chip ROM, and it can rapidly and flexibly deal with each situation on an application
system with fluid specifications from an early stage of mass production to full-scale production.
Note: F-ZTAT™ is a trademark of Renesas Technology Corp.
Target users: This manual was written for users who will be using the SH7055S F-ZTAT in
the design of application systems. Users of this manual are expected to
understand the fundamentals of electrical curcuits, logical circuits, and
microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of the SH7055S F-ZTAT to the above users.
Refer to the SH-2E Programming Manual for a detailed description of the
instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the SH-2E Programming Manual.
Rule:
Bit order: The MSB (most significant bit) is on the left and the LSB (least
significant bit) is on the right.
Releated Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
Rev.2.0, 07/03, page v of xxxviii
5 Page 
Item
Page Revisions (See Manual for Details)
11.2.22 Cycle Registers (CYLR) 335
wCwywc.ldeaRtaeshgeisette4rus.c(oCmYLR6A to
CYLR6D, CYLR7A to CYLR7D)
Description amended
At the same time, the buffer register (BFR) value is
transferred to the duty register (DTR). Output pin (TO6A
to TO6D, TO7A to TO7D) of corresponding channnel will
be 0 when H'0000 of BFR is 0 output and otherwise will
11.2.26 Channel 10 Registers 338 Description amended
Counters(TCNT)
Free-Running Counter 10AH,AL
…an input clock and is cleared to the initial value by input
capture input (TI10)(AGCK).
(TCNT10AH, TCNT10AL)
11.2.26 Channel 10 Registers 342 Description amended
Registers (TCNT)
Input Capture Register 10AH, AL
At the same time, ICF10A in timer status register 10
(TSR10) is set to 1.
(ICR10AH, ICR10AL)
11.3.1 Overview
355 Description amended
Channels 6 and 7
Do not set a value in DTR that will result in the condition
DTR > CYLR. When H'0000 is set to DTR, do not have
DTR directly read H'0000. Set BFR to H'0000 and set
H'0000 by forwarding from BFR to DTR. If H'0000 is
directly set to DTR, duty may not be 0%.
11.3.8 Twin-Capture Function 365 Description amended
Line 4
When TCNT0, TCNT1A, and TCNT2A in channel 0,
channel 1, and channel 2 are started by a setting in the
timer status register (TSR), and an edge detection is
carried out by the ICR0A input as a trigger signal, the
TCNT1A value is transferred to OSBR1, and the TCNT2A
value to OSBR2. Edge detection is as described in
section 11.3.4, Input Capture Function.
Rev.2.0, 07/03, page xi of xxxviii
11 Page | ||
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