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PDF HD64F7052F40 Data sheet ( Hoja de datos )
| Número de pieza | HD64F7052F40 | |
| Descripción | SuperHTM RISC engine | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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To all our customers
wwwR.deagtaashrdeeint4gu.ctohme change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
Preface
wTwhwe.dSaHta7s0h5ee2tF4/uS.cHo7m053F/SH7054F is a single-chip RISC (reduced instruction set computer)
microcomputer that has an original Hitachi RISC type CPU as its core, and also includes
peripheral functions necessary for system configuration.
The CPU of the SH7052F/SH7053F/SH7054F has a RISC type instruction set, with basic
instructions executed in one system clock cycle, for a higher instruction execution speed. It
employs an internal 32-bit configuration, and offers enhanced data processing performance. The
CPU of the SH7052F/SH7053F/SH7054F makes it possible to create high-performance, high-
functionality systems at low cost, even for applications requiring high speed such as real-time
control, which could not be realized with conventional microcomputers.
The SH7052F/SH7053F/SH7054F is also equipped with on-chip peripheral functions necessary
for system configuration, including large-capacity ROM and RAM, a direct memory access
controller (DMAC), timers, a serial communication interface (SCI), Hitachi controller area
network (HCAN), A/D converter, interrupt controller (INTC), and I/O ports.
In addition, an external memory access support function allows direct connection of ROM and
SRAM, enabling system costs to be greatly reduced.
The SH7052F/SH7053F/SH7054F is an F-ZTAT™ (Flexible Zero Turn-Around Time) version
with flash memory as its on-chip ROM. Flash memory programs can be written with a
programmer that supports SH7052F/SH7053F/SH7054F programming, and the flash memory can
also be programmed and erased by software. This allows reprogramming to be carried out by the
user with the chip mounted on a board.
This Hardware Manual describes the hardware of the SH7052F/SH7053F/SH7054F. Details of
instructions can be found in the Programming Manual.
Related Manual
Covering SH7052F/SH7053F/SH7054F execution instructions:
SH-1/SH-2/SH-DSP Programming Manual
Please consult your Hitachi sales representative for details of the development environment
system.
5 Page 
Contents
www.datasheet4u.com
Section 1 Overview ...........................................................................................................
1.1 Features..............................................................................................................................
1.2 Block Diagram...................................................................................................................
1.3 Pin Description ..................................................................................................................
1.3.1 Pin Arrangement ..................................................................................................
1.3.2 Pin Functions........................................................................................................
1.3.3 Pin Assignments ...................................................................................................
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1
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Section 2 CPU.....................................................................................................................
2.1 Register Configuration ......................................................................................................
2.1.1 General Registers (Rn) .........................................................................................
2.1.2 Control Registers..................................................................................................
2.1.3 System Registers ..................................................................................................
2.1.4 Initial Values of Registers ....................................................................................
2.2 Data Formats......................................................................................................................
2.2.1 Data Format in Registers......................................................................................
2.2.2 Data Format in Memory .......................................................................................
2.2.3 Immediate Data Format........................................................................................
2.3 Instruction Features ...........................................................................................................
2.3.1 RISC-Type Instruction Set ...................................................................................
2.3.2 Addressing Modes................................................................................................
2.3.3 Instruction Format ................................................................................................
2.4 Instruction Set by Classification........................................................................................
2.5 Processing States ...............................................................................................................
2.5.1 State Transitions ...................................................................................................
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Section 3 Operating Modes ............................................................................................ 53
3.1 Operating Mode Selection ................................................................................................. 53
Section 4 Clock Pulse Generator (CPG).....................................................................
4.1 Overview............................................................................................................................
4.1.1 Block Diagram......................................................................................................
4.1.2 Pin Configuration .................................................................................................
4.2 Frequency Ranges..............................................................................................................
4.3 Clock Source......................................................................................................................
4.3.1 Connecting a Crystal Oscillator............................................................................
4.3.2 External Clock Input Method ...............................................................................
4.4 Usage Notes .......................................................................................................................
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11 Page | ||
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| PDF Descargar | [ Datasheet HD64F7052F40.PDF ] | |
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