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PDF ISL6218 Data sheet ( Hoja de datos )
| Número de pieza | ISL6218 | |
| Descripción | Precision Single Phase Buck PWM Controller | |
| Fabricantes | Intersil | |
| Logotipo |  |
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®
Data Sheet
August 6, 2007
ISL6218
FN9101.6
Precision Single-Phase Buck PWM
Controller for Intel Mobile Voltage
Positioning IMVP-IV™ and IMVP-IV+™
The ISL6218 Single-Phase Buck PWM control IC, with
integrated half bridge gate driver, provides a precision
voltage regulation system for advanced Pentium-M
microprocessors in notebook computers. This control IC also
features both input voltage feed-forward and average current
mode control for excellent dynamic response, “Loss-less”
current sensing using MOSFET rDS(ON), and user selectable
switching frequencies from 250kHz to 500kHz per phase.
The ISL6218 includes a 6-bit digital-to-analog converter
(DAC) that dynamically adjusts the CORE PWM output
voltage from 0.700V to 1.708V in 16mV steps, and conforms
to the Intel IMVP-IV™ mobile VID specification. The ISL6218
also has logic inputs to select Active, Deep Sleep and
Deeper Sleep modes of operation. A precision reference,
remote sensing and proprietary architecture with integrated
processor-mode compensated “Droop” provides excellent
static and dynamic CORE voltage regulation.
Another feature of the ISL6218 IC controller is the internal
PGOOD delay circuit that holds the PGOOD pin low for
3ms to 12ms after the VCCP and VCC_MCH regulators are
within regulation. This PGOOD signal is masked during VID
changes. Output overvoltage and undervoltage are
monitored and result in the converter latching off and
PGOOD signal being held low.
The overvoltage and undervoltage thresholds are 112% and
84% of the VID, Deep or Deeper Sleep setpoint. Overcurrent
protection features a 32 cycle overcurrent shutdown.
PGOOD, Overvoltage, Undervoltage and Overcurrent
provide monitoring and protection for the microprocessor
and power system. The ISL6218 IC is available in a
38 Ld TSSOP and 40 Ld QFN package.
Features
• IMVP-IV™ Compliant CORE Regulator
• Single-Phase Power Conversion
• “Loss-less” Current Sensing for Improved Efficiency and
Reduced Board Area
- Optional Discrete Precision Current Sense Resistor
• Internal Gate Drive and Boot-Strap Diode
• Precision CORE Voltage Regulation
- 0.8% System Accuracy Over-temperature
• 6-Bit Microprocessor Voltage Identification Input
• Programmable “Droop” and CORE Voltage Slew Rate to
Comply with IMVP-IV™ Specification
• Discontinuous Mode Of Operation for Increased Light
Load Efficiency in Deep and Deeper Sleep Mode
• Direct Interface with System Logic (STP_CPU and
DPRSLPVR) for Deep and Deeper Sleep Modes of
Operation
• Easily Programmable Voltage Setpoints for Initial “Boot”,
Deep Sleep and Deeper Sleep Modes
• Excellent Dynamic Response
- Combined Voltage Feed-Forward and Average Current
Mode Control
• Overvoltage, Undervoltage and Overcurrent Protection
• Power-good Output with Internal Blanking During VID and
Mode Changes
• User Programmable Switching Frequency of 250kHz to
500kHz
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART NUMBER
PART MARKING
TEMP. RANGE (°C)
PACKAGE
PKG. DWG #
ISL6218CV*
ISL 6218CV
-10 to +85
38 Ld TSSOP
M38.173
ISL6218CVZ* (Note)
ISL 6218CVZ
-10 to +85
38 Ld TSSOP (Pb-free)
M38.173
ISL6218CVZA* (Note)
ISL 6218CVZ
-10 to +85
38 Ld TSSOP (Pb-free)
M38.173
ISL6218CRZ* (Note)
ISL62 18CRZ
-10 to +85
40 Ld 6x6 QFN (Pb-free) L40.6x6
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
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ISL6218
Functional Pin Description 38 Ld TSSOP
VDD
DACOUT
DSV
FSET
NC
EN
DRSEN
DSEN
VID0
VID1
VID2
VID3
VID4
VID5
PGOOD
EA+
COMP
FB
SOFT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
ISL6218
38 VBAT
37 ISEN
36 PHASE
35 UG
34 BOOT
33 VSSP
32 LG
31 VDDP
30 NC
29 NC
28 NC
27 NC
26 NC
25 NC
24 VSEN
23 DRSV
22 STV
21 OCSET
20 VSS
VDD
This pin is used to connect +5V to the IC to supply all power
necessary to operate the chip. The IC starts to operate when
the voltage on this pin exceeds the rising POR threshold and
shuts down when the voltage on this pin drops below the
falling POR threshold.
VDDP
This pin provides a low ESR bypass connection to the
internal gate drivers for the +5V source.
PGOOD
This pin is used as an input and an output and is tied to the
Vccp and Vcc_mch PGOOD signals. During start-up, this pin
is recognized as an input, and prevents further slewing of the
output voltage from the “Boot” level until PGOOD from Vccp
and Vcc_mch is enabled High. After start-up, this pin has an
open drain output used to indicate the status of the CORE
output voltage. This pin is pulled low when the system output
is outside of the regulation limits. PGOOD includes a timer
for power-on delay.
VSEN
This pin is used for remote sensing of the microprocessor
CORE voltage.
COMP
This pin provides connection to the error amplifier output.
FB
This pin is connected to the inverting input of the error
amplifier.
EA+
This pin is connected to the non-inverting input of the error
amplifier and is used for setting the “Droop” voltage.
STV
The voltage on this pin sets the initial start-up or “Boot”
voltage.
SOFT
This pin programs the slew rate of VID changes, Deep Sleep
and Deeper Sleep transitions, and soft-start after initializing.
This pin is connected to ground via a capacitor, and to EA+
through an external “Droop” resistor.
DSEN
This pin connects to system logic “STP_CPU” and enables
Deep Sleep mode of operation. Deep Sleep is enabled when
a logic LOW signal is detected on this pin.
DRSEN
This pin connects to system logic “DPRSLPVR” and enables
Deeper Sleep mode of operation when a logic HIGH is
detected on this pin.
VBAT
Voltage on this pin provides feed-forward battery information
that adjusts the oscillator ramp amplitude.
FSET
A resistor from this pin to ground programs the switching
frequency.
ISEN
This pin is used as current sense input from the converter
channel phase node.
EN
This pin is connected to the system signal VR_ON and
provides the enable/disable function for the PWM controller.
DACOUT
This pin provides access to the output of the Digital-to-
Analog Converter.
OCSET
A resistor from this pin to ground sets the overcurrent
protection threshold. The current from this pin should be
between 10µA and 25µA (70kΩ to 175kΩ equivalent
pull-down resistance).
DSV
The voltage on this pin provides the setpoint for output
voltage during Deep Sleep Mode of operation.
DRSV
The voltage on this pin provides the setpoint for output
voltage during Deeper Sleep Mode of operation.
5 FN9101.6
August 6, 2007
5 Page 
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VID[0..5]
CURRENT VID CODE
<600ns
VCC_CORE CURRENT VOLTAGE LEVEL
ISL6218
NEW VID CODE
NEW VOLTAGE LEVEL
PGOOD
HIGH
FIGURE 5. PLOT SHOWING TIMING OF VID CODE CHANGES AND CORE VOLTAGE SLEWING AS WELL AS PGOOD MASKING
VID[0..5]
VID CODE REMAINS THE SAME
STP_CPU
(DSEN)
VID COMMAND VOLTAGE
VCC_CORE
<3µs
VDEEP SLEEP
FIGURE 6. CORE VOLTAGE SLEWING TO 98.8% OF PROGRAMMED VID VOLTAGE FOR A LOGIC LEVEL LOW ON DSEN
VID[0..5]
VID CODE REMAINS THE SAME
STP_CPU
(DSEN)
DPRSLPVR
(DRSEN)
VCC_CORE
DEEPER SLEEP
SHORT DPRSLP CAUSES VCC_CORE TO RAMP-UP
VDEEP
VDEEPER
FIGURE 7. VCORE RESPONSE FOR DEEPER SLEEP COMMAND
Deep Sleep Enable (DSEN) and Deeper Sleep
Enable (DRSEN)
Table 2 shows logic states controlling modes of operation
Figure 6 and Figure 5 show the timing for transitions entering
and exiting Deep Sleep Mode and Deeper Sleep Mode,
controlled by the system signals STPCPU and DPRSLPVR.
Pins DSEN (Deep Sleep Enable) and DRSEN (Deeper
Sleep Enable) of the ISL6218 are connected to these 2
signals, respectively.
For the case when DSEN is logic high, and DRSEN is logic
low, the controller will operate in Active Mode and regulate
the output voltage to the VID commanded DAC voltage
minus the voltage “Droop” as determined by the load current.
Voltage “Droop” is the reduction of output voltage
proportional to output current.
When a logic low is seen on the DSEN and DRSEN is logic
low the controller will then regulate the output voltage to the
voltage seen on the DSV pin minus “Droop”.
When DSEN is logic low and DRSEN is logic high the
controller will operate in Deeper Sleep mode. The ISL6218
will then regulate to the voltage seen on the DRSV pin minus
“Droop”.
Deep and Deeper Sleep voltage levels are programmable
and explained in “STV, DSV and DRSV” on page 12.
DISCONTINUOUS OPERATION - PSI
The ISL6218 Single-Phase PWM controller is a
Synchronous Buck Regulator. However, in Deep and Deeper
Sleep modes where the load current is low, the controller
operates as a standard buck regulator. This mode of
operation acts to eliminate negative inductor current by
truncating the low side MOSFET gate drive pulse, and
11 FN9101.6
August 6, 2007
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ISL6218.PDF ] | |
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