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ISPXPGA の電気的特性と機能

ISPXPGAのメーカーはLattice Semiconductorです、この部品の機能は「ispXPGA Family」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISPXPGA
部品説明 ispXPGA Family
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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ISPXPGA Datasheet, ISPXPGA PDF,ピン配置, 機能
www.DataSheet4U.com
July 2008
Includes
High-
Performance,
Low-Cost
“E-Series”
ispXPGA® Family
Data Sheet DS1026
Non-volatile, Infinitely Reconfigurable
• Instant-on - Powers up in microseconds via
on-chip E2CMOS® based memory
• No external configuration memory
• Excellent design security, no bit stream to intercept
• Reconfigure SRAM based logic in milliseconds
High Logic Density for System-level
Integration
• 139K to 1.25M system gates
• 160 to 496 I/O
• 1.8V, 2.5V, and 3.3V VCC operation
• Up to 414Kb sysMEM™ embedded memory
High Performance Programmable Function
Unit (PFU)
• Four LUT-4 per PFU supports wide and narrow
functions
• Dual flip-flops per LUT-4 for extensive pipelining
• Dedicated logic for adders, multipliers, multiplex-
ers, and counters
Flexible Memory Resources
• Multiple sysMEM Embedded RAM Blocks
– Single port, Dual port, and FIFO operation
• 64-bit distributed memory in each PFU
– Single port, Double port, FIFO, and Shift
Register operation
Flexible Programming, Reconfiguration,
and Testing
• Supports IEEE 1532 and 1149.1
• Microprocessor configuration interface
• Program E2CMOS while operating from SRAM
Eight sysCLOCK™ Phase Locked Loops
(PLLs) for Clock Management
• True PLL technology
• 10MHz to 320MHz operation
• Clock multiplication and division
• Phase adjustment
• Shift clocks in 250ps steps
sysIO™ for High System Performance
• High speed memory support through SSTL and
HSTL
• Advanced buses supported through PCI, GTL+,
LVDS, BLVDS, and LVPECL
• Standard logic supported through LVTTL,
LVCMOS 3.3, 2.5 and 1.8
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL
interfaces
• Programmable drive strength for series termination
• Programmable bus maintenance
Two Options Available
• High-performance sysHSI (standard part number)
• Low-cost, no sysHSI (“E-Series”)
sysHSI™ Capability for Ultra Fast Serial
Communications
• Up to 800Mbps performance
• Up to 20 channels per device
• Built in Clock Data Recovery (CDR) and
Serialization and De-serialization (SERDES)
Table 1. ispXPGA Family Selection Guide
ispXPGA 125/E ispXPGA 200/E ispXPGA 500/E ispXPGA 1200/E
System Gates
139K
210K
476K
1.25M
PFUs
484
676
1764
3844
LUT-4s
1936
2704
7056
15376
Logic FFs
3.8K
5.4K
14.1K
30.7K
sysMEM Memory
92K
111K
184K
414K
Distributed Memory
30K
43K
112K
246K
EBR
20 24 40 90
sysHSI Channels1
4 8 12 20
User I/O
160/176
160/208
336
496
Packaging
256 fpBGA
516 fpBGA2
256 fpBGA
516 fpBGA2
516 fpBGA2
900 fpBGA
680 fpSBGA2
900 fpBGA
1. “E-Series” does not support sysHSI.
2. FH516 package was converted to F516 via PCN# 09A-08.
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
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DS1026_14.1

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ISPXPGA pdf, ピン配列
Lattice Semiconductor
ispXPGA Family Data Sheet
Awwrwc.DhaitatSehceettu4Ur.ceomOverview
The ispXPGA architecture is a symmetrical architecture consisting of an array of Programmable Function Units
(PFUs) enclosed by Input Output Groups (PICs) with columns of sysMEM Embedded Block RAMs (EBRs) distrib-
uted throughout the array. Figure 1 illustrates the ispXPGA architecture. Each PIC has two corresponding sysIO
blocks, each of which includes one input and output buffer. On two sides of the device, between the PICs and the
sysIO blocks, there are sysHSI High-Speed Interface blocks. The symmetrical architecture allows designers to eas-
ily implement their designs, since any logic function can be placed in any section of the device.
The PFUs contain the basic building blocks to create logic, memory, arithmetic, and register functions. They are
optimized for speed and flexibility allowing complex designs to be implemented quickly and efficiently.
The PICs interface the PFUs and EBRs to the external pins of the device. They allow the signals to be registered
quickly to minimize setup times for high-speed designs. They also allow connections directly to the different logic
elements for fast access to combinatorial functions.
The sysMEM EBRs are large, fast memory elements that can be configured as RAM, ROM, FIFO, and other stor-
age types. They are designed to facilitate both single and dual-port memory for high-speed applications.
These three components of the architecture are interconnected via a high-speed, flexible routing array. The routing
array consists of Variable Length Interconnect (VLI) lines between the PICs, PFUs, and EBRs. There is additional
routing available to the PFU for feedback and direct routing of signals to adjacent PFUs or PICs.
The sysIO blocks consist of configurable input and output buffers connected directly to the PICs. These buffers can
be configured to interface with 16 different I/O standards. This allows the ispXPGA to interface with other devices
without the need for external transceivers.
The sysHSI blocks provide the necessary components to allow the ispXPGA device to transfer data at up to
800Mbps using the LVDS standard. These components include serializing, de-serializing, and clock data recovery
(CDR) logic.
The sysCLOCK blocks provide clock multiplication/division, clock distribution, delay compensation, and increased
performance through the use of PLL circuitry that manipulates the global clocks. There is one sysCLOCK block for
each global clock tree in the device.
3


3Pages


ISPXPGA 電子部品, 半導体
Lattice Semiconductor
ispXPGA Family Data Sheet
Cwwown.DagtauShreaebt4lUe.cLomogic Element
The CLE is made up of a four-input Look-up Table (LUT-4), a Carry Chain Generator (CCG), and a two-input AND
gate. The LUT-4 creates various combinatorial and memory elements, the CCG creates a single one-bit full adder,
and the two-input AND gate can expand the CCG to incorporate Booth Multiplier capability by feeding the output of
the AND gate to one of the inputs of the CCG.
Of the five inputs that feed each CLE, two are dedicated inputs into each LUT-4 and the remaining three take on
varying functionality. The third and fourth inputs can be used as either inputs to the LUT-4 or as a Feed-Thru to the
CSE via the WLG. The fifth input can be a data port when the LUT is configured as Distributed Memory, a select
line for multiplexer operation, or a Feed-Thru directly to the CSE via the WLG (Figure 2).
Look-Up Table – Combinatorial Mode
In combinatorial mode, the LUT-4 can implement any logic function up to four inputs. By using the carry chain and
the WLG, each LUT-4 can be combined to form the enhanced functions listed in Table 3.
Look-Up Table – Distributed Memory Mode
In the distributed memory mode, the LUT functions as a memory element. The inputs to the LUT function as
Address and Data. Each PFU is capable of implementing up to 64 SRAM bits. Both single and double port RAM
can be performed in the PFU (Table 3). Furthermore, the distributed memory can be configured as either synchro-
nous or asynchronous memory. Figure 3 illustrates the LUT while in distributed memory mode. When using any
LUT in the PFU in memory mode, the Set/Reset signal will be used for Write Enable (WE(SR)) and the CLK0 signal
will be used as the clock for synchronous read and write.
Figure 3. LUT in Distributed Memory Mode
PFUCLK0
CEB0
WE (SR)
ADDR[0] (IN0)
ADDR[1] (IN1)
ADDR[2] (IN2)
ADDR[3] (IN3)
DIN (SEL)
LUT-4
DOUT (4A)
Look-Up Table – Shift Register Mode
In the shift register mode, the LUT functions as a 1-bit to 8-bit shift register. This means that each PFU can imple-
ment up to four 8-bit shift registers or any cascaded combination. Figure 4 illustrates the LUT when configured in
shift register mode.
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共有リンク

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部品番号部品説明メーカ
ISPXPGA

ispXPGA Family

Lattice Semiconductor
Lattice Semiconductor


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