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PDF 92R195B Data sheet ( Hoja de datos )
| Número de pieza | 92R195B | |
| Descripción | ST92R195B | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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ST92195B
32-64K ROM HCMOS MCU WITH
ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
DATA BRIEFING
s Register File based 8/16 bit Core Architecture
with RUN, WFI, SLOW and HALT modes
s 0°C to +70°C operating temperature range
s Up to 24 MHz. operation @ 5V±10%
s Min. instruction cycle time: 165ns at 24 MHz.
s 32, 48, 56 or 64 Kbytes ROM
s 256 bytes RAM of Register file (accumulators or
index registers)
s 256 bytes of on-chip static RAM
s 2, 6 or 8 Kbytes of TDSRAM (Teletext and
Display Storage RAM)
s 28 fully programmable I/O pins
s Serial Peripheral Interface
s Flexible Clock controller for OSD, Data Slicer
and Core clocks running from a single low
frequency external crystal.
s Enhanced display controller with 26 rows of
40/80 characters
– Serial and Parallel attributes
– 10x10 dot matrix, 512 ROM characters, defin-
able by user
– 4/3 and 16/9 supported in 50/60Hz and 100/
120 Hz mode
– Rounding, fringe, double width, double height,
scrolling, cursor, full background color, half-
intensity color, translucency and half-tone
modes
s Teletext unit, including Data Slicer, Acquisition
Unit and up to 8 Kbytes RAM for data storage
s VPS and Wide Screen Signalling slicer (on
some devices)
s Integrated Sync Extractor and Sync Controller
s 14-bit Voltage Synthesis for tuning reference
voltage
s Up to 6 external interrupts plus one Non-
Maskable Interrupt
s 8 x 8-bit programmable PWM outputs with 5V
open-drain or push-pull capability
s 16-bit watchdog timer with 8-bit prescaler
s One 16-bit standard timer with 8-bit prescaler
s 4-channel A/D converter; 5-bit guaranteed
PSDIP56
TQFP64
See end of document for ordering information
s Rich instruction set and 14 addressing modes
s Versatile development tools, including
Assembler, Linker, C-compiler, Archiver,
Source Level Debugger and hardware
emulators with Real-Time Operating System
available from third parties
s Pin-compatible EPROM and OTP devices
available
Device Summary
Device
ST92195B1
ST92195B2
ST92195B3
ST92195B4
ST92195B5
ST92195B6
ST92195B7
ST92T195B7
ST92E195B7
Program
Memory
32K ROM
32K ROM
32K ROM
48K ROM
48K ROM
56K ROM
64K ROM
64K OTP
64K EPROM
TDS
RAM
2K
6K
6K
6K
8K
8K
8K
8K
8K
VPS/
WSS
Package
Yes
No
Yes
Yes PSDIP56/
Yes TQFP64
Yes
Yes
Yes
Yes
CSDIP56
/CQFP64
Rev. 2.5
January 2000
1/22
1
1 page  
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1.2 PIN DESCRIPTION
Figure 2. 64-Pin Package Pin-Out
ST92195B - GENERAL DESCRIPTION
GND
AIN4/P0.2
P0.1
P0.0
CSO/RESET0/P3.7
P3.6
P3.5
P3.4
B
G
R
FB
SDO /SDI/ P5.1
INT2/SCK/P5.0
VDD
JTDO
64
1
16
N.C. = Not connected
48 VSS
P 4.7/P WM7/ EXTRG /STOUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3/TSLU/HT
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
HSYNC/CSYNC
AVDD1
PXFM
JTRST0
GND
N.C.
32
5/22
5 Page 
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ST92195B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
AF Outputs or Bidirectional Lines:
– In the case of Outputs or I/Os, AF is selected
explicitly by software.
Example 1: ADC trigger digital input
AF: EXTRG, Port: P4.7, Port Style: Standard I/O.
Write the port configuration bits (for TTL level):
P4C2.7=1
P4C1.7=0
P4C0.7=1
Enable the ADC trigger by software as described
in the ADC chapter.
Example 2: PWM 0 output
AF: PWM0, Port: P4.0
Write the port configuration bits (for output push-
pull):
P4C2.0=0
P4C1.0=1
P4C0.0=1
Example 3: ADC analog input
AF: AIN1, Port : P2.1, Port style: does not apply to
analog inputs
Write the port configuration bits:
P2C2.1=1
P2C1.1=1
P2C0.1=1
11/22
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| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet 92R195B.PDF ] | |
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