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PDF RTL8181 Data sheet ( Hoja de datos )
| Número de pieza | RTL8181 | |
| Descripción | Wireless LAN Access Point/Gateway Controller | |
| Fabricantes | ETC | |
| Logotipo |  |
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RTL8181 Wireless LAN Access Point/Gateway Controller
DATA SHEET
ISSUE 4: June 10, 2003
1 page  
www.DataSheet4U.com
Fast Ethernet Controller
? Fully compliant with IEEE 802.3/802.3u
? Support MII interface with full and half duplex capability
? Support descriptor-based buffer management with scatter-gather capability
? Support IP, TCP and UDP checksum offload
? Support IEEE 802.1Q VLAN tagging and 802.1P priority queue.
? Support full duplex flow control (IEEE 802.3X)
UART
? 16550 compatible
? 16 bytes FIFO size
? Auto CTS/RTS flow control
Memory Controller
? Support external 16/32-bit SDRAM with 2 banks access, up to 32M bytes
? Support external 16-bit Flash memory, up to 16M bytes
PCI Bridge
? Support two external PCI devices, complied with PCI 2.2
? Support PCI master/slave mode
? 3.3 and 5V I/O tolerance
GPIO
? 16 programmable I/O ports and more 16 port when memory interface is 16 bit mode.
? Individually configurable to input, output and edge transition
Watchdog/Timer/Counter
? A hardware watchdog timer, used to reset processor when system hangs up
? 4 sets of general timers/counters
EJTAG
? Standard P1149.1 JTAG interface for testing and debugging
2. Pin Description
Symbol Typ Pin No(208) Pin No(292) Description
e
Memory Interface
MD[31-0] I/O 198,197,195 P1,P2,N3,N Data for SDRAM, Flash.
,194,193,19 2,N1,M3,M
2,191,190,1 2,M1,L2,L3,
88,187,185, L1,K2,K3,K
184,182,181 1,J2,J1,H2,
,180,179,17 H1,G2,F1,G
7,176,174,1 3,F2,E1,F3,
73,171,170, E2,D1,D2,E
169,168,166 3,A1,B1,B2,
,165,163,16 C3
2,161,160,1
59,158
MA[21-0]/ O 115,116,118 B14,A15,D1 Address for SDRAM, Flash.
DQM[3-0]
,119,121,12 4,C14,A14, MA[15-18] mapping to DQM[3-0] for SDRAM
2,124,125,1 C13,B13,C1
27,128,130, 2,A12,C11,
131,133,134 B11,C10,A1
,135,136,13 1,B10,A10,
CONFIDENTIAL
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complete the current data phase transaction. This signal is used in conjunction
with the TRDYB signal. Data transaction takes place at the rising edge of CLK
when both IRDYB and TRDYB are asserted low. As a target, this signal indicates
that the master has put data on the bus.
TRDYB S/T/ *X
J19 Target Ready: This indicates the target agent’s ability to complete the current
S phase of the transaction.
As a bus master, this signal indicates that the target is ready for the data during
write operations and with the data during read operations. As a target, this signal
will be asserted low when the (slave) device is ready to complete the current data
phase transaction. This signal is used in conjunction with the IRDYB signal. Data
transaction takes place at the rising edge of CLK when both IRDYB and TRDYB
are asserted low.
PAR T/S *X R2 Parity: This signal indicates even parity across AD31-0 and C/BE3-0 including
the PAR pin. PAR is stable and valid one clock after each address phase. For data
phase, PAR is stable and valid one clock after either IRDYB is asserted on a
write transaction or TRDYB is asserted on a read transaction. Once PAR is valid,
it remains valid until one clock after the completion of the current data phase. As
a bus master, PAR is asserted during address and write data phases. As a target,
PAR is asserted during read data phases.
STOPB S/T/ *X
B16 Stop: Indicates that the current target is requesting the master to stop the current
S transaction.
RSTB O *X
B15 Reset: Active low signal to reset the PCI device.
MII Interface
LTXC, I 53,31
Y20
TXC is a continuous clock that provides a timing reference for the transfer of
WTXC
W11 TXD[3:0], TXE. In MII mode, it uses the 25 MHz or 2.5 MHz supplied by the
external PMD device.
LTXEN, O 59,37
T17
Indicates the presence of valid nibble data on TXD[3:0].
WTXEN
LTXD[3-0] O 57,56,55,54 V18,V17,W Four parallel transmit data lines which are driven synchronous t o the TXC for
, WTXD
35,34,33,32 19,W18 transmission by the external physical layer chip.
[3-0] V12,Y13,W
12,Y12
LRXC, I 51,29
W17,V11 This is a continuous clock that is recovered from the incoming data. MRXC is
WRXC
25MHz in 100Mbps and 2.5Mhz in 10Mbs.
LCOL, I 60,38
U18,V13 This signal is asserted high synchronously by the external physical unit upon
WCOL
detection of a collision on the medium. It will remain asserted as long as the
collision condition persists.
LRXDV, I 43,44
W16,W9 Data valid is asserted by an external PHY when receive data is present on the
WRXDV
RXD[3:0] lines, and it is deasserted at the end of the packet. This signal is valid
on the rising of the RXC.
LRXD[3-0 I 50,49,47,46 V15,V16,Y This is a group of 4 data signals aligned on nibble boundaries which are driven
], 27,26,24,23 18,Y17,Y11 synchronous to the RXC by the external physical unit
WRXD[3-
,W10,V10,
0] Y10
LRXER, I 44,22
V14,V9 This pin is asserted to indicate that invalid symbol has been detected in 100Mbps
WRXER
MII mode. This signal is synchronized to RXC and can be asserted for a
minimum of one receive clock.
LMDC, O 40,18
W15,W8 Management Data Clock: This pin provides a clock synchronous to MDIO,
WMDC
which may be asynchronous to the transmit TXC and receive RXC clocks.
LMDIO, I/O 41,19
Y16,Y9 Management Data Input/Output: This pin provides the bi-directional signal used
WMDIO
to transfer management information.
GPIO
GPIOB[11- I/O 205,206,207, U1,U2,U3, General purpose I/O pins group B pins 11 to 0. If ICFG[5-4] power on latch
0] 2,3,5,6,8,9,1 W1,Y1,Y2, =[1-0]. GPIO[5-2] mapping to JTAG_TDO(JTAG test data
1,12,13
W4,V5,Y4, output),JTAG_TRSTN(JTAG reset),JTAG_TMS(JTAG test mode
W5,V6,Y5 select),JTAG_TDI(JTAG test data input).
GPIOB[15 I/O 200,201,202, R1,T1,T2,T General purpose I/O pins group B pin 15 to 12.
-12] 203 3
CONFIDENTIAL
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v1.0
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