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PDF HD64F2128 Data sheet ( Hoja de datos )
| Número de pieza | HD64F2128 | |
| Descripción | (HD64321xx) Single-Chip Microcomputer | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
www.DataSheet4U.com
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
Preface
The H8S/2128 Series and H8S/2124 Series comprise high-performance microcomputers with a
32-bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system
configuration.
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The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen
internal 16-bit general registers with a 32-bit configuration, and a concise and optimized
instruction set. The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes).
Programs based on the high-level language C can also be run efficiently.
Single-power-supply flash memory (F-ZTAT™*) and mask ROM versions are available,
providing a quick and flexible response to conditions from ramp-up through full-scale volume
production, even for applications with frequently changing specifications.
On-chip peripheral functions include a 16-bit free-running timer module (FRT), 8-bit timer
module (TMR), watchdog timer module (WDT), two PWM timers (PWM and PWMX), a serial
communication interface (SCI), A/D converter (ADC), and I/O ports. An I2C bus interface (IIC)
can also be incorporated as an option.
An on-chip data transfer controller (DTC) is also provided, enabling high-speed data transfer
without CPU intervention.
The H8S/2128 Series has all the above on-chip supporting functions, and can also be provided
with an IIC module as an options. The H8S/2124 Series comprises reduced-function versions, with
fewer TMR, and no PWM, IIC, or DTC modules.
Use of the H8S/2128 or H8S/2124 Series enables compact, high-performance systems to be
implemented easily. The various timer functions and their interconnectability (timer connection),
plus the interlinked operation of the I2C bus interface and data transfer controller (DTC), in
particular, make these devices ideal for use in PC monitors. In addition, the combination of F-
ZTATTM and reduced-function versions is ideal for system applications in which on-chip program
memory is essential to meet performance requirements, product start-up times are short, and
program modifications may be necessary after end-product assembly.
This manual describes the hardware of the H8S/2128 Series and H8S/2124 Series. Refer to the
H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the
instruction set.
Note: * F-ZTATTM (Flexible-ZTAT) is a trademark of Hitachi, Ltd.
5 Page 
2.8.6 Power-Down State ................................................................................................ 66
2.9 Basic Timing ...................................................................................................................... 67
2.9.1 Overview ............................................................................................................... 67
2.9.2 On-Chip Memory (ROM, RAM) .......................................................................... 67
2.9.3 On-Chip Supporting Module Access Timing........................................................ 69
2.9.4 External Address Space Access Timing................................................................ 70
2.10 Uwswawge.DNatoatSeh.e..e..t.4.U.....c.o..m........................................................................................................... 70
2.10.1 TAS Instruction ..................................................................................................... 70
2.10.2 STM/LDT Instruction ........................................................................................... 70
Section 3 MCU Operating Modes.................................................................................... 73
3.1 Overview ............................................................................................................................ 73
3.1.1 Operating Mode Selection .................................................................................... 73
3.1.2 Register Configuration .......................................................................................... 74
3.2 Register Descriptions.......................................................................................................... 74
3.2.1 Mode Control Register (MDCR) .......................................................................... 74
3.2.2 System Control Register (SYSCR) ....................................................................... 75
3.2.3 Bus Control Register (BCR) ................................................................................. 77
3.2.4 Serial/Timer Control Register (STCR) ................................................................. 78
3.3 Operating Mode Descriptions ............................................................................................ 80
3.3.1 Mode 1 .................................................................................................................. 80
3.3.2 Mode 2 .................................................................................................................. 80
3.3.3 Mode 3 .................................................................................................................. 80
3.4 Pin Functions in Each Operating Mode.............................................................................. 81
3.5 Memory Map in Each Operating Mode.............................................................................. 81
Section 4 Exception Handling........................................................................................... 89
4.1 Overview ............................................................................................................................ 89
4.1.1 Exception Handling Types and Priority................................................................ 89
4.1.2 Exception Handling Operation.............................................................................. 90
4.1.3 Exception Sources and Vector Table .................................................................... 90
4.2 Reset ................................................................................................................................... 92
4.2.1 Overview ............................................................................................................... 92
4.2.2 Reset Sequence...................................................................................................... 92
4.2.3 Interrupts after Reset ............................................................................................. 94
4.3 Interrupts ............................................................................................................................ 95
4.4 Trap Instruction .................................................................................................................. 96
4.5 Stack Status after Exception Handling ............................................................................... 97
4.6 Notes on Use of the Stack .................................................................................................. 98
Section 5 Interrupt Controller............................................................................................ 99
5.1 Overview ............................................................................................................................ 99
5.1.1 Features ................................................................................................................. 99
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| PDF Descargar | [ Datasheet HD64F2128.PDF ] | |
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