PDF IS62WV25616BLL Data sheet ( Hoja de datos )

Número de pieza	IS62WV25616BLL
Descripción	ULTRA LOW POWER CMOS STATIC RAM
Fabricantes	Integrated Silicon Solution
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No Preview Available ! IS62WV25616ALL IS62WV25616BLL 256K x 16 LOWwww.DataSheet4U.com VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM ISSI® MAY 2005 FEATURES • High-speed access time: 55ns, 70ns • CMOS low power operation 36 mW (typical) operating 9 µW (typical) CMOS standby • TTL compatible interface levels • Single power supply 1.65V--2.2V VDD (IS62WV25616ALL) 2.5V--3.6V VDD (IS62WV25616BLL) • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial temperature available • Lead-free available FUNCTIONAL BLOCK DIAGRAM DESCRIPTION The ISSI IS62WV25616ALL/IS62WV25616BLL are high- speed, low power, 4M bit SRAMs organized as 256K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high- performance and low power consumption devices. When CS1 is HIGH (deselected) or when CS1 is LOW and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62WV25616ALL/IS62WV25616BLL are packaged in the JEDEC standard 44-Pin TSOP (TYPE II) and 48-pin mini BGA (6mmx8mm). A0-A17 VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte DECODER I/O DATA CIRCUIT 256K x 16 MEMORY ARRAY COLUMN I/O CS1 OE CONTROL WE CIRCUIT UB LB Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 1 1 page IS62WV25616ALL, IS62WV25616BLL CwwAwP.DAatCaSIhTeeAt4NU.CcoEm (1) Symbol Parameter Conditions Max. Unit CIN Input Capacitance VIN = 0V 8 pF COUT Input/Output Capacitance VOUT = 0V 10 pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load IS62WV25616ALL (Unit) 0.4V to VDD-0.2V 5 ns VREF See Figures 1 and 2 IS62WV25616BLL (Unit) 0.4V to VDD-0.3V 5ns VREF See Figures 1 and 2 ISSI ® R1(Ω) R2(Ω) VREF VTM IS62WV25616ALL 1.65V-2.2V 3070 3150 0.9V 1.8V IS62WV25616BLL 2.5V - 3.6V 3070 3150 1.5V 2.8V AC TEST LOADS VTM R1 OUTPUT Figure 1 30 pF Including jig and scope R2 VTM R1 OUTPUT Figure 2 5 pF Including jig and scope R2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 5 5 Page IS62WV25616ALL, IS62WV25616BLL ISSI ® DwAwTwA. RD EaTt EaNSThIOe Ne tS4WU I.TcCoHmING CHARACTERISTICS Symbol VDR IDR tSDR tRDR Parameter Test Condition VDD for Data Retention Data Retention Current See Data Retention Waveform VDD = 1.2V, CS1 ≥ VDD – 0.2V Data Retention Setup Time See Data Retention Waveform Recovery Time See Data Retention Waveform Min. Max. 1.2 3.6 — 15 0— tRC — Unit V µA ns ns DATA RETENTION WAVEFORM (CS1 Controlled) VDD VDR CS1 GND tSDR Data Retention Mode CS1 ≥ VDD - 0.2V tRDR Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 11 11 Page

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