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EE87C196Kx の電気的特性と機能

EE87C196KxのメーカーはIntelです、この部品の機能は「User Manual」です。


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部品番号 EE87C196Kx
部品説明 User Manual
メーカ Intel
ロゴ Intel ロゴ 




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EE87C196Kx Datasheet, EE87C196Kx PDF,ピン配置, 機能
8XC196Lx Supplement to
8XC196Kx, 8XC196Jx,
87C196CA User’s Manual
August 2004
Order Number: 272973-003

1 Page





EE87C196Kx pdf, ピン配列
CONTENTS
CHAPTER 1
wGwUwI.DDEataTSOheTeHt4IUS.cMoAmNUAL
1.1 MANUAL CONTENTS ................................................................................................... 1-1
1.2 RELATED DOCUMENTS .............................................................................................. 1-2
CHAPTER 2
ARCHITECTURAL OVERVIEW
2.1 MICROCONTROLLER FEATURES .............................................................................. 2-1
2.2 BLOCK DIAGRAM......................................................................................................... 2-2
2.3 INTERNAL TIMING........................................................................................................ 2-2
2.4 EXTERNAL TIMING ...................................................................................................... 2-5
2.5 INTERNAL PERIPHERALS ........................................................................................... 2-6
2.5.1 I/O Ports ....................................................................................................................2-7
2.5.2 Synchronous Serial I/O Port .....................................................................................2-7
2.5.3 Event Processor Array ..............................................................................................2-7
2.5.4 J1850 Communications Controller ............................................................................2-7
2.6 DESIGN CONSIDERATIONS........................................................................................ 2-7
CHAPTER 3
ADDRESS SPACE
3.1 ADDRESS PARTITIONS ............................................................................................... 3-1
3.2 REGISTER FILE ............................................................................................................ 3-2
3.3 PERIPHERAL SPECIAL-FUNCTION REGISTERS ...................................................... 3-4
3.4 WINDOWING................................................................................................................. 3-6
CHAPTER 4
STANDARD AND PTS INTERRUPTS
4.1 INTERRUPT SOURCES, VECTORS, AND PRIORITIES ............................................. 4-1
4.2 INTERRUPT REGISTERS............................................................................................. 4-2
4.2.1 Interrupt Mask Registers ...........................................................................................4-3
4.2.2 Interrupt Pending Registers ......................................................................................4-4
4.2.3 Peripheral Transaction Server Registers ..................................................................4-6
CHAPTER 5
I/O PORTS
5.1 I/O PORTS OVERVIEW ................................................................................................ 5-1
5.2 INTERNAL STRUCTURE FOR PORTS 1, 2, 5, AND 6 (BIDIRECTIONAL PORTS) .... 5-1
5.2.1 Configuring Ports 1, 2, 5, and 6 (Bidirectional Ports) ................................................5-3
5.2.2 Special Bidirectional Port Considerations .................................................................5-4
5.3 INTERNAL STRUCTURE FOR PORTS 3 AND 4 (ADDRESS/DATA BUS).................. 5-5
iii


3Pages


EE87C196Kx 電子部品, 半導体
8XC196LX SUPPLEMENT
FIGURES
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Figure
Page
2-1 8XC196Lx Block Diagram ............................................................................................2-2
2-2 Clock Circuitry (87C196LA, LB Only) ...........................................................................2-3
2-3 Internal Clock Phases (Assumes PLL is Bypassed).....................................................2-4
2-4 Effect of Clock Mode on Internal CLKOUT Frequency.................................................2-5
2-5 Unerasable PROM 1 (USFR1) Register (LA, LB Only) ................................................2-6
3-1 Register File Address Map ...........................................................................................3-3
4-1 Interrupt Mask (INT_MASK) Register...........................................................................4-3
4-2 Interrupt Mask 1 (INT_MASK1) Register......................................................................4-4
4-3 Interrupt Pending (INT_PEND) Register ......................................................................4-5
4-4 Interrupt Pending 1 (INT_PEND1) Register .................................................................4-6
4-5 PTS Select (PTSSEL) Register ....................................................................................4-7
4-6 PTS Service (PTSSRV) Register .................................................................................4-8
5-1 Ports 1, 2, 5, and 6 Internal Structure (87C196LA, LB Only) .......................................5-3
5-2 Ports 3 and 4 Internal Structure (87C196LA, LB Only) ................................................5-6
6-1 SSIO 0 Clock (SSIO0_CLK) Register...........................................................................6-1
6-2 SSIO 1 Clock (SSIO1_CLK) Register...........................................................................6-2
7-1 EPA Block Diagram (87C196LA, LB Only)...................................................................7-2
7-2 EPA Block Diagram (83C196LD Only) .........................................................................7-3
7-3 EPA Interrupt Mask (EPA_MASK) Register .................................................................7-4
7-4 EPA Interrupt Mask 1 (EPA_MASK1) Register ............................................................7-4
7-5 EPA Interrupt Pending (EPA_PEND) Register.............................................................7-5
7-6 EPA Interrupt Pending 1 (EPA_PEND1) Register........................................................7-5
7-7 EPA Interrupt Priority Vector Register (EPAIPV)..........................................................7-6
8-1 Integrated J1850 Communications Protocol Solution...................................................8-1
8-2 J1850 Communications Controller Block Diagram .......................................................8-2
8-3 Huntzicker Symbol Definition for J1850........................................................................8-7
8-4 Typical VPW Waveform................................................................................................8-7
8-5 Bit Arbitration Example .................................................................................................8-8
8-6 J1850 Message Frames ...............................................................................................8-9
8-7 Huntzicker Symbol Definition for the Normalization Bit ..............................................8-10
8-8 Definition for Start and End of Frame Symbols ..........................................................8-11
8-9 IFR Type 1 Message Frame.......................................................................................8-12
8-10 IFR Type 2 Message Frame.......................................................................................8-13
8-11 IFR Type 3 Message Frame.......................................................................................8-13
8-13 J1850 Transmit Message Structure............................................................................8-14
8-12 J1850 Transmitter (J_TX) Register ............................................................................8-14
8-15 J1850 Receive Message Structure.............................................................................8-15
8-14 J1850 Receiver (J_RX) Register ................................................................................8-15
8-16 J1850 Command (J_CMD) Register ..........................................................................8-17
8-17 J1850 Configuration (J_CFG) Register ......................................................................8-18
8-18 J1850 Delay (J_DLY) Register ...................................................................................8-20
8-19 J1850 Status (J_STAT) Register................................................................................8-21
9-1 Reset Source (RSTSRC) Register ...............................................................................9-1
10-1 Clock Circuitry (87C196LA, LB Only) .........................................................................10-2
vi

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部品番号部品説明メーカ
EE87C196KC

User Manual

Intel
Intel
EE87C196Kx

User Manual

Intel
Intel


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