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53NC50のメーカーはSTMicroelectronicsです、この部品の機能は「 STE53NC50」です。 |
部品番号 | 53NC50 |
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部品説明 | STE53NC50 | ||
メーカ | STMicroelectronics | ||
ロゴ | |||
このページの下部にプレビューと53NC50ダウンロード(pdfファイル)リンクがあります。 Total 8 pages
www.DataSheet4U.com
STE53NC50
N-CHANNEL 500V - 0.070Ω - 53A ISOTOP
PowerMesh™II MOSFET
TYPE
VDSS
RDS(on)
ID
STE53NC50
500V
< 0.08Ω
53 A
n TYPICAL RDS(on) = 0.07 Ω
n EXTREMELY HIGH dv/dt CAPABILITY
n 100% AVALANCHE TESTED
n NEW HIGH VOLTAGE BENCHMARK
n GATE CHARGE MINIMIZED
DESCRIPTION
The PowerMESH™II is the evolution of the first
generation of MESH OVERLAY™. The layout re-
finements introduced greatly improve the Ron*area
figure of merit while keeping the device at the lead-
ing edge for what concerns swithing speed, gate
charge and ruggedness.
ISOTOP
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
n HIGH CURRENT, HIGH SPEED SWITCHING
n SWITH MODE POWER SUPPLIES (SMPS)
n DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVER
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDS Drain-source Voltage (VGS = 0)
VDGR
Drain-gate Voltage (RGS = 20 kΩ)
VGS Gate- source Voltage
ID Drain Current (continuos) at TC = 25°C
ID Drain Current (continuos) at TC = 100°C
IDM (l) Drain Current (pulsed)
PTOT
Total Dissipation at TC = 25°C
Derating Factor
dv/dt (1) Peak Diode Recovery voltage slope
VISO
Insulation Winthstand Voltage (AC-RMS)
Tstg Storage Temperature
Tj Max. Operating Junction Temperature
(•)Pulse width limited by safe operating area
May 2002
Value
500
500
±30
53
33
212
460
3.68
3
2500
– 65 to 150
150
(1) ISD≤ 53A, di/dt≤100 A/µs, VDD≤ 24V, Tj≤TjMAX
Unit
V
V
V
A
A
A
W
W/°C
V/ns
V
°C
°C
1/8
1 Page www.DataSheet4U.com
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol
Parameter
Test Conditions
td(on)
tr
Turn-on Delay Time
Rise Time
VDD = 250V, ID = 26.5A
RG = 4.7Ω VGS = 10V
(see test circuit, Figure 3)
Qg Total Gate Charge
Qgs Gate-Source Charge
VDD = 400V, ID = 53A,
VGS = 10V
Qgd Gate-Drain Charge
SWITCHING OFF
Symbol
Parameter
tr(Voff)
Off-voltage Rise Time
tf Fall Time
tc Cross-over Time
Test Conditions
VDD = 400V, ID = 53A,
RG = 4.7Ω, VGS = 10V
(see test circuit, Figure 5)
SOURCE DRAIN DIODE
Symbol
Parameter
Test Conditions
ISD Source-drain Current
ISDM (2) Source-drain Current (pulsed)
VSD (1) Forward On Voltage
ISD = 53A, VGS = 0
trr
Qrr
IRRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 53A, di/dt = 100A/µs,
VDD = 70V, Tj = 150°C
(see test circuit, Figure 5)
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
STE53NC50
Min.
Typ.
46
70
310
46
150
Max.
434
Unit
ns
ns
nC
nC
nC
Min.
Typ.
45
38
85
Max.
Unit
ns
ns
ns
Min.
Typ.
760
17.86
47
Max.
53
212
1.6
Unit
A
A
V
ns
µC
A
Safe Operating Area
Thermal Impedence
3/8
3Pages STE53NC50
www.DataSheet4U.com
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/8
6 Page | |||
ページ | 合計 : 8 ページ | ||
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部品番号 | 部品説明 | メーカ |
53NC50 | STE53NC50 | STMicroelectronics |