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PDF D3-6402R-9Z Data sheet ( Hoja de datos )
| Número de pieza | D3-6402R-9Z | |
| Descripción | HD3-6402R-9Z | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
CMOS Universal Asynchronous
Receiver Transmitter (UART)
The HD-6402 is a CMOS UART for interfacing computers or
microprocessors to an asynchronous serial data channel.
The receiver converts serial start, data, parity and stop bits.
The transmitter converts parallel data into serial form and
automatically adds start, parity and stop bits. The data word
length can be 5, 6, 7 or 8 bits. Parity may be odd or even.
Parity checking and generation can be inhibited. The stop
bits may be one or two or one and one-half when
transmitting 5-bit code.
The HD-6402 can be used in a wide range of applications
including modems, printers, peripherals and remote data
acquisition systems. Utilizing the Intersil advanced scaled
SAJI IV CMOS process permits operation clock frequencies
up to 8.0MHz (500K Baud). Power requirements, by
comparison, are reduced from 300mW to 10mW. Status
logic increases flexibility and simplifies the user interface.
Pinout
HD-6402 (PDIP, CERDIP)
TOP VIEW
VCC 1
NC 2
GND 3
RRD 4
RBR8 5
RBR7 6
RBR6 7
RBR5 8
RBR4 9
RBR3 10
RBR2 11
RBR1 12
PE 13
FE 14
OE 15
SFD 16
RRC 17
DRR 18
DR 19
RRI 20
40 TRC
39 EPE
38 CLS1
37 CLS2
36 SBS
35 PI
34 CRL
33 TBR8
32 TBR7
31 TBR6
30 TBR5
29 TBR4
28 TBR3
27 TBR2
26 TBR1
25 TRO
24 TRE
23 TBRL
22 TBRE
21 MR
October 31, 2005
HD-6402
FN2956.3
Features
• 8.0MHz Operating Frequency (5962-9052502)
• 2.0MHz Operating Frequency (HD3-6402R)
• Low Power CMOS Design
• Programmable Word Length, Stop Bits and Parity
• Automatic Data Formatting and Status Generation
• Compatible with Industry Standard UARTs
• Single +5V Power Supply
• CMOS/TTL Compatible Inputs
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
TEMP 2MHz = 125K
PACKAGE RANGE (°C)
BAUD
8MHz = 500K
BAUD
PKG.
DWG.
#
PDIP
-40 to +85 HD3-6402R-9
E40.6
PDIP*
(Pb-free)
-40 to +85 HD3-6402R-9Z
(Note)
E40.6
CERDIP - -55 to +125
SMD#
5962-
F40.6
9052502MQA
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
HD-6402
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RRI
RBR1-8, OE, PE
DRR
DR
FE
BEGINNING OF FIRST STOP BIT
7 1/2 CLOCK CYCLES
1 CLOCK CYCLE
A BC
FIGURE 2. RECEIVER TIMING (NOT TO SCALE)
START BIT
5-8 DATA BITS
1, 11/2 OR 2 STOP BITS
LSB MSB †
FIGURE 3. SERIAL DATA FORMAT
PARITY
† IF ENABLED
Start Bit Detection
The receiver uses a 16X clock timing. The start bit could have
occurred as much as one clock cycle before it was detected,
as indicated by the shaded portion (A). The center of the start
bit is defined as clock count 7 1/2. If the receiver clock is a
symmetrical square wave, the center of the start bit will be
located within ±1/2 clock cycle, ±1/32 bit or 3.125% giving a
receiver margin of 46.875%. The receiver begins searching
for the next start bit at the center of the first stop bit.
CLOCK
RRI INPUT
A
Interfacing with the HD-6402
START
71/2 CLOCK CYCLES
81/2 CLOCK CYCLES
FIGURE 4.
COUNT 71/2 DEFINED
CENTER OF START BIT
DIGITAL
SYSTEM
TRANSMITTER
TBR1
TBR8
TRO
CONTROL
HD-6402
CONTROL
RB1
RRI
RB8
RECEIVER
RS232
DRIVER
RS232
RECEIVER
RS232
RECEIVER
RS232
DRIVER
RECEIVER
RB1
RRI RB8
CONTROL
HD-6402
CONTROL
TRO
TBR1
TBR8
TRANSMITTER
FIGURE 5. TYPICAL SERIAL DATA LINK
5
DIGITAL
SYSTEM
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