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PDF AT25640B Data sheet ( Hoja de datos )
| Número de pieza | AT25640B | |
| Descripción | SPI Automotive Temperature Serial EEPROMs | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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AT25080B, AT25160B, AT25320B, and AT25640B
SPI Automotive Temperature Serial EEPROMs
8K (1,024 x 8), 16K (2,048 x 8), 32K (4,096 x 8), 64K (8,192 x 8)
Features
DATASHEET
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
̶ Datasheet Describes Mode 0 Operation
Low-voltage, Medium-voltage and High-voltage Operation
̶ Grade 1, VCC = 2.5V to 5.5V
̶ Grade 2(1) and 3, VCC = 1.7V to 5.5V
Extended Temperature Range (Grade 1, 2(1), and 3 as defined in AEC-Q100)
̶ Grade 1 Temperature Range: -40C to 125C
̶ Grade 2 Temperature Range(1): -40C to 105C
̶ Grade 3 Temperature Range: -40C to 85C
5MHz Clock Rate
32-byte Page Mode
Block Write Protection
̶ Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and
Software Data Protection
Self-timed Write Cycle (5ms max)
High Reliability
̶ Endurance: 1,000,000 Write Cycles
̶ Data Retention: 100 Years
8-lead JEDEC SOIC, 8-lead TSSOP, and 8-pad UDFN Packages
Note: 1. Contact Sales for Grade 2 Availability
Description
The Atmel® AT25080B/160B/320B/640B provides 8,192/16,384/32,768/65,536
bits of Serial Electrically-Erasable Programmable Read-Only Memory (EEPROM)
organized as 1,024/2,048/4,096/8,192 words of 8 bits each. The device is
optimized for use in many automotive applications where low-power and
low-voltage operation are essential. AT25080B/160B/320B/640B is available in
space-saving 8-lead JEDEC SOIC, 8-lead TSSOP, and 8-pad UDFN packages.
AT25080B/160B/320B/640B is enabled through the Chip Select pin (CS) and
accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data
Output (SO), and Serial Clock (SCK). All programming cycles are completely
self-timed, and no separate erase cycle is required before write.
Block Write protection is enabled by programming the status register with one of
four blocks of write protection. Separate program enable and program disable
instructions are provided for additional data protection. Hardware data protection
is provided via the WP pin to protect against inadvertent write attempts to the
status register. The HOLD pin may be used to suspend any serial communication
without resetting the serial sequence.
Atmel-8803E-SEEPROM-AT25080B-160B-320B-640B-Auto-Datasheet_092016
1 page  
4. Serial Interface Description
Master: The device that generates the serial clock.
Slave: Because the Serial Clock pin (SCK) is always an input, AT25080B/160B/320B/640B always operates as
a slave.
Transmitter/Receiver: AT25080B/160B/320B/640B has separate pins designated for data transmission (SO)
and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
Serial Opcode: After the device is selected with CS going low, the first byte will be received. This byte contains
the opcode that defines the operations to be performed.
Invalid Opcode: If an invalid opcode is received, no data will be shifted into AT25080B/160B/320B/640B, and
the Serial Output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again.
This will reinitialize the serial communication.
Chip Select: AT25080B/160B/320B/640B is selected when the CS pin is low. When the device is not selected,
data will not be accepted via the SI pin, and the Serial Output pin (SO) will remain in a high impedance state.
Hold: The HOLD pin is used in conjunction with the CS pin to select AT25080B/160B/320B/640B. When the
device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication
with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while
the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low
(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high
impedance state.
Write Protect: The Write Protect pin (WP) will allow normal read/write operations when held high. When the
WP pin is brought low and WPEN bit is one, all write operations to the status register are inhibited. WP going
low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is
blocked when the WPEN bit in the status register is zero. This will allow the user to install
AT25080B/160B/320B/640B in a system with the WP pin tied to ground and still be able to write to the status
register. All WP pin functions are enabled when the WPEN bit is set to one.
AT25080B/160B/320B/640B Automotive [DATASHEET]
Atmel-8803E-SEEPROM-AT25080B-160B-320B-640B-Auto-Datasheet_092016
5
5 Page 
Write Sequence (Write): In order to program AT25080B/160B/320B/640B, two separate instructions must be
executed. First, the device must be write enabled via the WREN instruction. Then a write instruction may be
executed. Also, the address of the memory location(s) to be programmed must be outside the protected
address field location selected by the Block Write protection level. During an internal write cycle, all commands
will be ignored except the RDSR instruction.
A write instruction requires the following sequence. After the CS line is pulled low to select the device, the write
opcode is transmitted via the SI line followed by the byte address (A15A0) and the data (D7 – D0) to be
programmed (See Table 6-6). Programming will start after the CS pin is brought high. The low-to-high transition
of the CS pin must occur during the SCK low-time immediately after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR)
instruction. If Bit 0 = one, the write cycle is still in progress. If Bit 0 = zero, the write cycle has ended. Only the
RDSR instruction is enabled during the write programming cycle.
AT25080B/160B/320B/640B is capable of a 32-byte page write operation. After each byte of data is received,
the five low-order address bits are internally incremented by one; the high-order bits of the address will remain
constant. If more than 32 bytes of data are transmitted, the address counter will roll-over and the previously
written data will be overwritten. AT25080B/160B/320B/640B is automatically returned to the Write Disable state
at the completion of a write cycle.
Note: If the device is not Write Enabled (WREN), the device will ignore the write instruction and will return to
the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial
communication.
Table 6-6. Address Key
Address
AN
Don’t Care Bits
AT25080B
A9–A0
A15–A10
AT25160B
A10–A0
A15–A11
AT25320B
A11–A0
A15–A12
AT25640B
A12–A0
A15–A13
AT25080B/160B/320B/640B Automotive [DATASHEET]
Atmel-8803E-SEEPROM-AT25080B-160B-320B-640B-Auto-Datasheet_092016
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet AT25640B.PDF ] | |
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