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PDF ISL6341C Data sheet ( Hoja de datos )
| Número de pieza | ISL6341C | |
| Descripción | 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller | |
| Fabricantes | Intersil Corporation | |
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ISL6341, ISL6341A, ISL6341B, ISL6341C
®
www.DataSheet4U.com
Data Sheet
December 2, 2008
FN6538.2
5V or 12V Single Synchronous Buck
Pulse-Width Modulation (PWM) Controller
The ISL6341, ISL6341A, ISL6341B, ISL6341C makes
simple work out of implementing a complete control and
protection scheme for a DC/DC stepdown converter driving
N-Channel MOSFETs in a synchronous buck topology. Since
it can work with either 5V or 12V supplies, this one family of
IC’s can be used in a wide variety of applications within a
system. It integrates the control, gate drivers, output
adjustment, monitoring and protection functions into a single
10 Ld Thin DFN package.
The ISL6341, ISL6341A, ISL6341B, ISL6341C (hereafter
referred to as “ISL6341x”, except as needed) provides single
feedback loop, voltage-mode control with fast transient
response. The output voltage can be precisely regulated to as
low as 0.8V, with a maximum tolerance of ±0.8%
over-temperature and line voltage variations. A fixed frequency
oscillator and wide duty cycle range reduces design complexity,
while balancing typical application cost and efficiency. The
frequency, duty cycle and OCP response are the only
differences among the ISL6341x versions. See Table 1.
Protection from overcurrent conditions is provided by
monitoring the rDS(ON) of the lower MOSFET to inhibit PWM
operation appropriately (see “Overcurrent Protection (OCP)”
on page 8 for details). This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense resistor. The output voltage is also
monitored for undervoltage and overvoltage protection, in
addition to monitoring for a PGOOD output.
Ordering Information
PART NUMBER PART
TEMP.
PACKAGE
(Note)
MARKING RANGE (°C) (Pb-free)
PKG.
DWG. #
ISL6341ACRZ* 41AC
0 to +70 10 Ld 3x3 TDFN L10.3x3B
ISL6341BCRZ* 41BC
0 to +70 10 Ld 3x3 TDFN L10.3x3B
ISL6341CCRZ* 41CC
0 to +70 10 Ld 3x3 TDFN L10.3x3B
ISL6341CRZ* 341C
0 to +70 10 Ld 3x3 TDFN L10.3x3B
ISL6341AIRZ* 41AI
-40 to +85 10 Ld 3x3 TDFN L10.3x3B
ISL6341BIRZ* 41BI
-40 to +85 10 Ld 3x3 TDFN L10.3x3B
ISL6341CIRZ* 41CI
-40 to +85 10 Ld 3x3 TDFN L10.3x3B
ISL6341IRZ* 6341
-40 to +85 10 Ld 3x3 TDFN L10.3x3B
ISL6341EVAL1Z Evaluation Board
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel
specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• Operates from +4.5V to 14.4V Supply Voltage (for Bias)
- 1.5V to 12V VIN Input Range (Up to 20V is Possible with
Restrictions; see “Input Voltage Considerations” on
page 12)
- 0.8V to ~VIN Output Range (Duty Cycle Limited)
- Integrated Gate Drivers; LGATE Uses VCC (5V to 12V);
UGATE Uses External Boot Diode to (5V to 12V)
- 0.8V Internal Reference; ±0.8% Tolerance
• Simple Single-Loop Control Design
- Traditional Dual Edge Modulator
- Voltage-Mode PWM Control
- Drives N-Channel MOSFETs
• Fast Transient Response
- High-Bandwidth Error Amplifier
- 0% to 85% Max Duty Cycle for ISL6341, ISL6341C
- 0% to 75% Max Duty Cycle for ISL6341A, ISL6341B
• Lossless, Programmable Overcurrent Protection
- Uses Lower MOSFET’s rDS(ON)
- Latch off mode (ISL6341, ISL6341B)
- Infinite Retry (Hiccup) Mode (ISL6341A)
- Infinite Retry (Hiccup) Mode; no UVP (ISL6341C)
• Output Voltage Monitoring
- Undervoltage and Overvoltage Shutdown
- PGOOD Output
• Small Converter Size in 10 Ld 3x3 Thin DFN
- 300kHz Fixed Oscillator (ISL6341, ISL6341C)
- 600kHz Fixed Oscillator (ISL6341A, ISL6341B)
- Fixed Internal Soft-Start, Capable into a Pre-biased
Load
- Enable/Shutdown Function on COMP/EN Pin
• Pb-Free (RoHS Compliant)
Applications
• Power Supplies for Microprocessors or Peripherals
- PCs, Servers, Memory Supplies
- DSP and Core Communications Processor Supplies
• Subsystem Power Supplies
- PCI, AGP; Graphics Cards; Digital TV
- SSTL-2 and DDR/DDR2/DDR3 SDRAM Bus
Termination Supply
• Cable Modems, Set-Top Boxes, and DSL Modems
• Industrial Power Supplies; General Purpose Supplies
• 5V or 12V-Input DC/DC Regulators
• Low-Voltage Distributed Power Supplies; Point of Load
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2007, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6341, ISL6341A, ISL6341B, ISL6341C
Electrical Specifications
www.DataSheet4U.com
PARAMETER
Test Conditions: VCC = 12V, TJ = 0°C to +85°C, Unless Otherwise Noted. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested. (Continued)
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Upper Gate Sink Impedance
Lower Gate Source Impedance
Lower Gate Sink Impedance
PROTECTION/DISABLE
RUG-SNKl
RLG-SRCl
RLG-SNKl
VCC = 5V; I = 50mA
VCC = 5V; I = 50mA
VCC = 5V; I = 50mA
1.7 Ω
1.5 Ω
1.1 Ω
OCSET Current Source
Enable Threshold (COMP/EN pin)
VOS Rising Trip (PGOOD OV; +10%)
IOCSET LGATE/OCSET = 0V
VENABLE
9
0.683
0.868
10
0.700
0.880
11
0.717
0.888
µA
V
V
VOS Rising Trip (PGOOD OV) Hysteresis
16 mV
VOS Falling Trip (PGOOD UV; -10%)
0.708 0.720 0.732
V
VOS Falling Trip (PGOOD UV) Hysteresis
16 mV
VOS Rising Threshold (OV; +25%)
0.980 1.000 1.020
V
VOS Falling Threshold (UV; -25%)
(Note 5)
0.580 0.600 0.620
V
VOS Threshold (OV; 50% of VOUT)
VOS Bias Current
VOS = 0.25V
0.380
-1500
0.400
-250
0.410
-100
V
nA
PGOOD
NOTES:
IPGOOD = 4mA
0.10 0.18 0.30
V
3. Limits should be considered typical and are not production tested.
4. Limits established by characterization and are not production tested.
5. The UVP is disabled on the ISL6341C; no trip point is measured.
Functional Pin Description
VCC (Pin 6)
This pin provides the bias supply for the ISL6341x, as well
as the lower MOSFET’s gate. An internal regulator will
supply bias as VCC rises above 5V, but the LGATE/OCSET
will still be sourced by VCC. Connect a well-decoupled 5V to
12V supply to this pin.
FB (Pin 8)
This pin is the inverting input of the internal error amplifier. Use
FB, in combination with the COMP/EN pin, to compensate the
voltage-control feedback loop of the converter. A resistor divider
from VOUT to FB to GND is used to set the regulation voltage.
VOS (Pin 9)
This input pin monitors the regulator output for OV and UV
protection, and PGOOD (OV and UV). Connect a resistor
divider from VOUT to VOS to GND, with the same ratio as
the FB resistor divider. It is not recommended to share one
divider for both FB and VOS; the response to a fault may not
be as quick or robust. There is a small pull-up bias current
on the pin; if the VOS pin is not connected, the OV protection
would be tripped to protect the load.
GND (Pin 5)
This pin represents the signal and power ground for the IC.
This pin is the high current connection, and should be tied to
the ground island/plane through the lowest impedance
connection available. The metal pad under the package
should also be connected to the GND plane for thermal
conductivity, but does not conduct any current.
PHASE (Pin 2)
Connect this pin to the source of the upper MOSFET, and
the drain of the lower MOSFET. It is used as the sink for the
UGATE driver, and to monitor the voltage drop across the
lower MOSFET for overcurrent protection. This pin is also
monitored by the adaptive shoot-through protection circuitry
to determine when the upper MOSFET has turned off.
UGATE (Pin 3)
Connect this pin to the gate of upper MOSFET; it provides
the PWM-controlled gate drive. It is also monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
BOOT (Pin 1)
This pin provides ground referenced bias voltage to the upper
MOSFET driver. A bootstrap circuit is used to create a voltage
suitable to drive an N-Channel MOSFET (equal to VGD minus
the BOOT diode voltage drop), with respect to PHASE.
COMP/EN (Pin 7)
This is a multiplexed pin. During soft-start and normal converter
operation, this pin represents the output of the error amplifier.
Use COMP/EN, in combination with the FB pin, to compensate
the voltage-control feedback loop of the converter.
5 FN6538.2
December 2, 2008
5 Page 
ISL6341, ISL6341A, ISL6341B, ISL6341C
PGOOD
The PGOOD function output monitors the output voltage
uswinwgwth.DeastaaSmheeeVt4OUS.cpomin and resistor divider of the
undervoltage and overvoltage protection, but with separate
comparators for each. The rising OV trip point (10% above
0.8V = 0.88V nominal on VOS) and the falling UV trip point
(10% below 0.8V = 0.72V nominal on VOS) will trip sooner
than the protection, in order to give an early warning to a
possible problem. The response time of the comparators
should be less than 1µs; the separate VOS input is not slowed
down by the compensation on the FB pin. It is NOT
recommended to connect the VOS pin to the FB pin, in order
to share the resistor divider. If the VOS pin is accidentally
disconnected, a small bias current on-chip will force an
overvoltage condition.
Figure 9 shows how the PGOOD output responds to a ramp
that trips in each direction (without reaching either protection
trip point at ±25%); PGOOD is valid (high) as long as VOUT
(and thus VOS) is within the ±10% window.
110%
90%
VOUT (0.25V/DIV)
GND>
PGOOD (2V/DIV)
GND>
FIGURE 9. PGOOD UNDERVOLTAGE AND OVERVOLTAGE
The PGOOD output is an open-drain pull-down NMOS
device; it can deliver 4.0mA of sink current at 0.3V when
power is NOT GOOD. A pull-up resistor to an external supply
voltage sets the high level voltage when power is GOOD. The
supply should be ≤6.0V, and is usually the one that powers
the logic monitoring the PGOOD output. If PGOOD function is
not used, the PGOOD pin can be left floating.
The PGOOD pin will be held low once VCC is above the rising
POR trip point, and during soft-start (but if the PGOOD supply
is up before or with VCC, it may be pulled high initially until the
logic has enough voltage to turn on the output). Once the
soft-start ramp is done (VOUT, VOS and FB should each be at
100% of their final value), the PGOOD pin will be allowed to
go high, if the output voltage is within the expected window.
There is no additional delay after soft-start is done.
Note that the overcurrent protection does directly affect the
PGOOD output, before the output voltage monitoring would
sense when VOUT drops 10%. The overvoltage and
undervoltage protection circuits don’t directly effect PGOOD,
but since the PGOOD UV and OV windows are tighter, the
PGOOD output should already be low by the time either
protection is tripped.
TABLE 2. PROTECTION SUMMARY
PROTECTION
ACTION TAKEN
ENABLED RESET
AFTER
BY
OCP
ISL6341
ISL6341B
VOUT latches off;
LGATE and UGATE low.
POR or POR or
COMP/EN COMP/EN
OCP
ISL6341A
ISL6341C
Infinite retries; wait ~10ms, POR or Not
and try a new Soft-Start ramp. COMP/EN Applicable
ISL6341C has UVP disabled
UVP
(-25%)
VOUT latches off;
LGATE and UGATE low.
after SS
ramp
ISL6341C has UVP disabled
POR
OVP
(+25%)
VOUT latches off;
UGATE low;
POR
LGATE goes low and high to
keep VOUT within 50% and
125% of nominal.
VOS pin open will trigger OV.
POR
PGOOD
(UV; -10%)
PGOOD goes low if VOS is after SS
10% too low.
ramp
POR or
COMP/EN
PGOOD
(OV; +10%)
PGOOD goes low if VOS is after SS
10% too high.
ramp
POR or
COMP/EN
PGOOD
(OCP)
PGOOD goes low if OCP trips after SS
ramp
POR or
COMP/EN
or good
SS ramp
Switching Frequency
The switching frequency is a fixed 300kHz for the ISL6341,
ISL6341C and 600kHz for the ISL6341A, ISL6341B. It
cannot be adjusted externally, and the various soft-start
delays and ramps are fixed at the same times for either
frequency.
Output Voltage Selection
The output voltage can be programmed to any level between
the 0.8V internal reference, up to the VIN supply, with the
85% duty cycle restriction for the ISL6341, ISL6341C (75%
for the ISL6341A, ISL6341B). Additional duty cycle margin
due to the rDS(ON) drop across the upper FET at maximum
load needs to be factored in as well.
An external resistor divider is used to scale the output
voltage relative to the internal reference voltage, and feed it
back to the inverting input of the error amp. See the “Typical
Application” schematic on page 3 for more detail; RS is the
upper resistor; ROFFSET (shortened to RO below) is the
lower one. The recommended value for RS is 1kΩ to 5kΩ
(±1% for accuracy) and then ROFFSET is chosen according
to Equation 2. Since RS is part of the compensation circuit
(see “Feedback Compensation” on page 13), it is often
easier to change ROFFSET to change the output voltage;
that way the compensation calculations do not need to be
11 FN6538.2
December 2, 2008
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ISL6341C.PDF ] | |
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