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ISL6537 の電気的特性と機能

ISL6537のメーカーはIntersil Corporationです、この部品の機能は「ACPI Regulator/Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL6537
部品説明 ACPI Regulator/Controller
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL6537 Datasheet, ISL6537 PDF,ピン配置, 機能
®
Data Sheet
February 8, 2005
ISL6537
FN9142.4
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6537 provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller to
supply VDDQ during S0/S1 and S3 states. During S0/S1
state, a fully integrated sink-source regulator generates an
accurate (VDDQ/2) high current VTT voltage without the
need for a negative supply. A buffered version of the VDDQ/2
www.DataShereeft4eUre.cnocme is provided as VREF. Two LDO controllers are also
integrated for the GMCH core voltage regulation and for the
GMCH and CPU VTT termination voltage regulation.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. The switching
regulator provides a maximum static regulation tolerance of
±2% over line, load, and temperature ranges. The output is
user-adjustable by means of external resistors down to 0.8V.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the VIDPGD signal
indicates that the GMCH and CPU VTT termination voltage
is within spec and operational.
Each output is monitored for undervoltage events. The
switching regulator also has overvoltage and over current
protection. Thermal shutdown is integrated.
Pinout
ISL6537 (6x6 QFN)
TOP VIEW
28 27 26 25 24 23 22
5VSBY 1
21 DRIVE4
S3# 2
20 REFADJ4
P12V 3
GND 4
DDR_VTT 5
GND
29
19 DRIVE3
18 FB3
17 FB4
DDR_VTT 6
16 COMP
VDDQ 7
15 FB
8 9 10 11 12 13 14
Features
• Generates 4 Regulated Voltages
- Synchronous Buck PWM Controller for DDR VDDQ
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference for DDR VTT
- LDO Regulator for GMCH Core
- LDO Regulator for CPU/GMCH VTT Termination
• ACPI compliant sleep state control
• Glitch-free Transitions During State Changes
• Integrated VREF Buffer
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
- All Outputs: ±2% Over Temperature
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Over-voltage Monitoring on All Outputs
• OCP on the Switching Regulator
• Integrated Thermal Shutdown Protection
• Pb-Free Available (RoHS Compliant)
Applications
Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
Graphics cards - GPU and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
Ordering Information
TEMP. RANGE
PART NUMBER
(°C)
PACKAGE
PKG.
DWG. #
ISL6537CR
0 to 70
28 Ld 6x6 QFN L28.6x6
ISL6537CRZ
(See Note)
0 to 70
28 Ld 6x6 QFN L28.6x6
(Pb-free)
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL6537 pdf, ピン配列
ISL6537
Simplified Power System Diagram
5VSBY
12V
VDDQ
SLP_S3
SLP_S5
Q3
VGMCH
www.DataSheet4U.com
Q4
+
Q5
VTT_GMCH/CPU
+
SLEEP
STATE
LOGIC
TWO STAGE
LINEAR
CONTROLLER
PWM
CONTROLLER
ISL6537
LINEAR
CONTROLLER
VTT
REGULATOR
5VDUAL
Q1
VDDQ
+
Q2
VREF
VTT
+
Typical Application
5VSBY 12V
5VDUAL
VDDQ_DDR
Q3
SLP_S5
SLP_S3
VGMCH
Q4
R5
R6
Q5
VTT_GMCH/CPU
R7
R8
VIDPGD
S5#
S3#
DRIVE4
FB4
REFADJ4
DRIVE3
FB3
BOOT
ISL6537
OCSET
UGATE
PHASE
LGATE
DDR_VDDQ(x2)
COMP
DRIVE2
FB
DBOOT
ROCSET
CBOOT
C1
R2 C2
R4
VREF_OUT
FB2
VREF_IN
Q1
Q2
R3 C3
R1
VDDQ_DDR
+
VREF
GND
DDR_VTT(x2)
DDR_VTTSNS
VTT_DDR
3 FN9142.4
February 8, 2005


3Pages


ISL6537 電子部品, 半導体
ISL6537
Functional Pin Description
5VSBY (Pin 1)
5VSBY is the bias supply of the ISL6537. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6537 enters a reduced
power mode and draws less than 1mA (ICC_S5) from the
5VSBY supply. The supply to 5VSBY should be locally
bypassed using a 0.1µF capacitor.
P12V (Pin 3)
The VTT regulation circuit and the Linear Drivers are
powered by P12V. P12V is not required during S3/S4/S5
operation. P12V is typically connected to the +12V rail of an
www.DataSheAeTt4XUp.coowmer supply.
GND (Pins 4, 27, 29)
The GND terminals of the ISL6537 provide the return path
for the VTT LDO, and switching MOSFET gate drivers. High
ground currents are conducted directly through the exposed
paddle of the QFN package which must be electrically
connected to the ground plane through a path as low in
inductance as possible.
UGATE (Pin 26)
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the upper MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
LGATE (Pin 28)
Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the lower
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the lower MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
FB (Pin 15) and COMP (Pin 16)
The VDDQ switching regulator employs a single voltage
control loop. FB is the negative input to the voltage loop error
amplifier. The VDDQ output voltage is set by an external
resistor divider connected to FB. With a properly selected
divider, VDDQ can be set to any voltage between the power
rail (reduced by converter losses) and the 0.8V reference.
Loop compensation is achieved by connecting an AC
network across COMP and FB.
The FB pin is also monitored for under and over-voltage
events.
PHASE (Pin 24)
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET
for over-current protection.
OCSET (Pin 22)
Connect a resistor (ROCSET) from this pin to the drain of the
upper MOSFET. ROCSET, an internal 20µA current source
(IOCSET), and the upper MOSFET on-resistance (rDS(ON))
set the converter over-current (OC) trip point according to
the following equation:
IPEAK = I--O-----C----S---r-E-D---T-S---x-(--RO-----ON----)C----S----E----T--
An over-current trip cycles the soft-start function.
VDDQ (Pins 7, 8)
The VDDQ pins should be connected externally together to
the regulated VDDQ output. During S0/S1 states, the VDDQ
pins serve as inputs to the VTT regulator and to the VTT
Reference precision divider.
DDR_VTT (Pins 5, 6)
The DDR_VTT pins should be connect externally together.
During S0/S1 states, the DDR_VTT pins serve as the
outputs of the VTT linear regulator. During S3 state, the VTT
regulator is disabled.
DDR_VTTSNS (Pin 9)
VTTSNS is used as the feedback for control of the VTT linear
regulator. Connect this pin to the VTT output at the physical
point of desired regulation.
VREF_OUT (Pin 13)
VREF_OUT is a buffered version of VTT and also acts as the
reference voltage for the VTT linear regulator. It is
recommended that a minimum capacitance of 0.1µF is
connected between VDDQ and VREF_OUT and also
between VREF_OUT and ground for proper operation.
VREF_IN (Pin 14)
A capacitor, CSS, connected between VREF_IN and ground
is required. This capacitor and the parallel combination of
the Upper and Lower Divider Impedance (RU||RL), sets the
time constant for the start up ramp when transitioning from
S3/S4/S5 to S0/S1/S2.
The minimum value for CSS can be found through the
following equation:
CSS > C---1--V-0---T----T-2--O-A----U----T-R-----U--V---|-D|---R-D---L-Q---
The calculated capacitance, CSS, will charge the output
capacitor bank on the VTT rail in a controlled manner without
reaching the current limit of the VTT LDO.
6 FN9142.4
February 8, 2005

6 Page



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共有リンク

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