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PDF A6285 Data sheet ( Hoja de datos )
| Número de pieza | A6285 | |
| Descripción | 16-Channel Constant-Current Latched LED Driver | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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A6285
16-Channel Constant-Current Latched LEDDriver
with Open LED Detection and Dot Correction
Features and Benefits
▪ 3.0 to 5.5 V logic supply range
▪ Schmitt trigger inputs for improved noise immunity
▪ Power-On Reset (POR)
▪ Up to 80 mA constant-current sinking outputs
▪ LED open circuit detection (LOD)
▪ Dot correction (DC) for adjusting LED light intensity on
each channel with 7-bit resolution
www.DataShee▪t4UL.coowm-power CMOS logic and latches
▪ High data input rate up to 30 MHz
▪ Active output pull-ups with enable/disable
▪ 20 ns typical staggering delay between outputs
▪ Internal UVLO and thermal shutdown (TSD) circuitry
▪ Fault output flags for an LED open circuit (LOD) or a
thermal shutdown (TSD) condition
Package: 32 Contact QFN (suffix ET)
5 mm × 5 mm
0.90 mm nominal overall height
Not to scale
Description
The A6285 is designed for LED display applications. This
BiCMOS device includes an On/Off shift register, a Dot
Correction (DC) shift register, accompanying data latches, and
16 MOS constant-current sink drivers with active pull-ups that
can be enabled or disabled as required by the application.
The CMOS shift registers and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, typical serial data input rates can reach up to 30 MHz.
The LED drive current level can be set by a single external
resistor, selected by the application designer. A CMOS serial
data output permits cascading of multiple devices in applications
requiring additional drive lines.
Individual LED light intensity can be adjusted to correct for light
intensity variations by using the Dot Correction feature.
Open LED connections can be detected, and then signaled back
to the host microprocessor through the serial data output (SDO
pin). The FAULT output flags an LED open circuit (LOD)
condition or a thermal shutdown (TSD) condition.Astaggering
delay on the load outputs during ON/OFF transitions helps to
reduce ground bounce.
Continued on the next page…
Typical Application
VDD VLED
VLED
Controller
SDI
FAULT
CLK
LE
MODE
OE
100 KΩ
SDI
FAULT
CLK
LE
MODE
OE
PE OUT0
A6285
10 μF
OUT15
SDO
VDD
100 nF
REXT
SDO
6285-DS
1 page  
A6285
16-Channel Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
Operating Characteristics
ELECTRICAL CHARACTERISTICS at TA1 = 25°C, VDD = 3.0 to 5.5 V, unless otherwise noted
Characteristic
Symbol
Test Conditions
Min.
Typ.2
Max.
Unit
Logic Supply Voltage Range
LED Load Supply Output Voltage
Undervoltage Lockout
www.DataSheet4U.com
Output Current
Output to Output Matching Error4
VDD
VLED
VDD(UV)
IO
Err
Operating
Operating
VDD 0 → 5.0 V
VDD 5 → 0.0 V
VDS = 1 V, REXT = 600 Ω
VDS = 1 V, REXT = 1.2 kΩ
1 V = VDS(x), REXT = 600 Ω;
All outputs on
1 V = VDS(x), REXT = 1.2 kΩ;
All outputs on
3.0 5.0 5.5
V
– – 12.0 V
2.5 2.7 2.9
V
2.3 2.5 2.7
V
70 80 90 mA
35 40 45 mA
–
+1.0
+4.0
%
–
+1.0
+4.0
%
Load Regulation
∆IOreg
VDS(X) = 1 to 3 V, REXT = 600 Ω;
All outputs on
– – +6.0 %
Output Leakage Current
Logic Input Voltage
Logic Input Voltage Hysteresis
Logic Input Current
SDO Voltage
Supply Current3
IDSS VOH = 12 V
– – 0.5 μA
VIH
0.8×VDD
–
VDD
V
VIL
GND
– 0.2×VDD V
VIhys All digital inputs
250 – 900 mV
II All digital inputs
–1 –
1 μA
VOL IOL = 1 mA
– – 0.5 V
VOH IOH = –1 mA
VDD – 0.5
–
–
V
IDD(OFF)
REXT = 9.6 kΩ, VOE = 5 V
REXT = 1.2 kΩ, VOE = 5 V
– – 6 mA
– – 17 mA
IDD(ON)
All outputs on, REXT = 1.2 kΩ, VO = 1 V,
data transfer 30 MHz
All outputs on, REXT = 600 Ω, VO = 1 V,
data transfer 30 MHz
–
–
– 25 mA
26 35 mA
FAULT Output
VOUT(0) IOUT = 5 mA; faults asserted
IOUT(1) VOUT = 5.5 V, open drain; faults negated
–
–
– 0.4
–1
Active Pull-up
IOUT(0) VLED = 1 V, all outputs off
– 2.8 –
Thermal Shutdown Temperature
TJTSD Temperature increasing
– 165 –
Thermal Shutdown Hysteresis
TJTSDhys
– 15 –
Open LED Detection Threshold
VLOD
– 0.30 0.40
Reference Voltage at REXT
VEXT REXT = 600 Ω
1.21 1.25 1.31
1Tested at 25°C. Specifications are assured by design and characterization over the operating temperature range of –40°C to 85°C.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
3Recommended operating range: VO = 1.0 to 3.0 V.
4Err = (IO(min or max) – IO(av)) / IO(av).
V
μA
mA
°C
°C
V
V
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
5 Page 
A6285
16-Channel Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
temperature, TTSDF, of 165°C (typical), all driver outputs will
be turned off and a TSD fault will be flagged. The TSD flag will
pull the FAULT output pin to PGND (low). After a 15°C (typi-
cal) drop in junction temperature, the outputs will turn back on
and the FAULT pin will be pulled back to VDD (high). The input
shift register and the latch register will remain active during a
TSD event. Therefore, there is no need to reset the data in the
output latches. However, the TSD cycle will continue until the
thermal problem is corrected.
w w w LE. DDOpaent DaeteSctihone(LOe Dt) T4heUA62. 85c proovimdes LED open
circuit detection. This circuit flags a fault and pulls the FAULT
pin to PGND (low) if any of the 16 OUTx LEDs are open or
disconnected from the circuit.
The LOD circuit flags a fault when all of the following conditions
are met:
• O¯¯E¯ is set low
• The voltage at each OUTx pin is sampled after being turned on
• VOUTx < VLOD (0.3 V typical)
MODE may be set either high or low. However, to perform a
complete LOD cycle, which includes reading the LOD status of
each OUTx, MODE must be set low.
A complete LOD cycle is described as follows:
the input shift register every time On/Off data is moved into
the On/Off Register, although in reality, the previous LOD
status is being moved into the input shift register.
If an LOD condition was previously detected, a 1 for each
open LED will be moved from the Open Circuit Detector into
the input shift register, where it can be read on the SDO pin.
4. The existing LOD condition is sampled within 2 μs of the out-
puts turning on and the resulting status data waits at the Open
Circuit Detector until moved into the input shift register on the
rising edge of the next LE pulse.
5. The cycle is repeated when new On/Off data is clocked into
the input shift register. As new data is being clocked in, LOD
status data is being clocked out of the SDO pin, where it can
be read by a microprocessor.
Note: It is not necessary to load new On/Off data in order to view
the LOD status waiting at the Open Circuit Detector. A second
LE pulse will put the LOD data into the input shift register. How-
ever, LOD data that is presently in the input shift register will be
moved into the On/Off Register, generating a “blank” display.
Such a blank display may be undesirable; therefore, a second
LE pulse should not be applied without first clocking in useful
On/Off data for updating the display.
1. On/Off data is clocked into the input shift register.
2. LE is pulsed to move the On/Off data into the On/Off Reg-
ister. The data is moved on the rising edge of LE. If an LOD
condition is present, the FAULT output is immediately pulled
to PGND (low).
3. Data present at the Open Circuit Detector (sampled when data
was moved into the On/Off Register on the previous transition
of LE) is immediately moved into the input shift register on
the same rising edge of LE.
The update interval between LE pulses ( LE1 to LE2 ), referred
to as the LOD Sample and Read Time, tLOD, must be at least
1660 ns to allow for settling and staggered delays. Figure 11
shows the LOD serial data format. The FAULT truth table is
shown below.
LSB MSB
…0
LOD
1
LOD
14 15
LOD
LOD
SDO
If no LOD condition was previously detected, all 0s are pres-
ent at the Open Circuit Detector. Thus, all 0s are moved into
the input shift register. This gives the appearance of “clearing”
OUT0
OUT1 through OUT14
OUT15
Figure 11. Individual output LOD data format
FAULT Truth Table
Junction Temperature
TJ < TTSD
TJ < TTSD
TJ < TTSD
TJ < TTSD
TJ > TTSD
TJ > TTSD
TJ > TTSD
TJ > TTSD
Conditions
Outx Voltage
Outx > VLOD
Outx < VLOD
Outx > VLOD
Outx < VLOD
Outx > VLOD
Outx < VLOD
Outx > VLOD
Outx < VLOD
Output Enable, O¯¯E¯
H
H
L
L
H
H
L
L
Fault Output
H
H
H
L
L
L
L
L
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet A6285.PDF ] | |
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