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A6282 の電気的特性と機能

A6282のメーカーはAllegro MicroSystemsです、この部品の機能は「16-Channel Constant-Current LED Driver」です。


製品の詳細 ( Datasheet PDF )

部品番号 A6282
部品説明 16-Channel Constant-Current LED Driver
メーカ Allegro MicroSystems
ロゴ Allegro MicroSystems ロゴ 




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A6282 Datasheet, A6282 PDF,ピン配置, 機能
A6282
16-Channel Constant-Current LEDDriver
Features and Benefits
16 constant-current outputs, up to 50 mA each
LED output voltage up to 12 V
3.0 to 5.5 V logic supply range
Schmitt trigger inputs for improved noise immunity
Power-On Reset (POR), all register bits = 0
Low-power CMOS logic and latches
High data input rate: 30 MHz
Output current accuracy: between channels < ±3% and
between ICs ±7%, over the full operating temperature
range
Internal UVLO and thermal shutdown (TSD) circuitry
Packages:
24-pin TSSOP
with exposed thermal pad
(Package LP)
Not to scale
24-contact QFN
4 mm × 4 mm × 0.75 mm
(Package ES)
Description
TheA6282 device is designed for LED display applications.This
CMOS device includes an input shift register, accompanying
data latches, and 16 MOS constant current sink drivers.
The CMOS shift registers and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, typical serial data input rates can reach up to 30 MHz.
The LED drive current level can be set by a single external
resistor, selected by the application designer. A serial data
output permits cascading of multiple devices in applications
requiring additional drive lines.
The A6282 is available in two 24-terminal packages: QFN
(package ES) and TSSOP (LP), which have an exposed
thermal pad. Both packages are lead (Pb) free with 100% matte
tin leadframe plating.
Applications include the following:
Monocolor, multicolor, or full-color LED display
Monocolor, multicolor, or full-color LED signboard
Display backlighting
Multicolor LED lighting
SDI
Controller
CLK
LE
OE
Typical Application
VLED
10 μF
SDI OUT0
OUT15
SDO
CLK VDD VDD
LE A6282
100 nF
GND
OE
REXT
IC 1
SDI
CLK
LE
OE
10 μF
OUT0
A6282
OUT15 SDO
VDD VDD
100 nF
GND
REXT
IC 2
6282-DS, Rev. 4
Cascaded A6282 devices

1 Page





A6282 pdf, ピン配列
A6282
16-Channel Constant-Current LED Driver
Functional Block Diagram
VDD
SDI
CLK
UVLO and TSD
Serial - Parallel Shift Register
OE Control Logic
LE Block
Latches
Output Control Drivers
REXT
IO
Regulator
Exposed Pad
(ET and LP packages)
GND OUT0 OUT1
SDO
OUT15
VLED
CLK, SDI,
LE, O¯¯E¯
Inputs and Outputs Equivalent Circuits
Resistor values are equivalent resistance and not tested
VDD
500 Ω
10 Ω
VDD
SDO
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3


3Pages


A6282 電子部品, 半導体
A6282
16-Channel Constant-Current LED Driver
ELECTRICAL CHARACTERISTICS (continued), at TA1 = 25°C, VDD = 3.0 to 5.5 V, unless otherwise noted
Characteristic
Symbol
Test Conditions
Min.
Typ.2
Max.
Unit
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Reference Voltage at External
Resistor REXT
TJTSD Temperature increasing
TJTSDhys
VEXT REXT = 374
– 165 –
– 15 –
– 1.21 –
°C
°C
V
1Tested at 25°C. Specifications are assured by design and characterization over the operating temperature range of –40°C to 85°C.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
3Err = (IO(min or max) – IO(av)) / IO(av). IO(av) is the average current of all outputs. IO(min or max) is the output current with the greatest
difference from IO(av).
4Recommended operating range: VO = 1.0 to 3.0 V.
SWITCHING CHARACTERISTICS at TA1 = 25°C, VDD = VIH = 5.0 V, VDS = 1 V, VIL = 0 V, REXT = 910 Ω, IO = 21.4 mA, VL = 2 V,
RL = 51 Ω, CL = 15 pF (see also Timing Diagrams section)
Characteristic
Symbol
Test Conditions
Min.
Typ.2 Max.
Unit
Clock Frequency
fCLK CLK
– – 30 MHz
Clock Frequency (cascaded devices)
fCLKC CLK
– – 25 MHz
Clock Pulse Duration
twh0 CLK = high
16 –
– ns
LE Pulse Duration
twh1 LE = high
20 –
– ns
Setup Time
tsu0 SDI to CLK
tsu1 CLKto LE
10 –
10 –
– ns
– ns
Hold Time
th0 CLKto SDI
th1 LEto CLK
10 –
10 –
– ns
– ns
Rise Time
Fall Time
Propagation Delay Time
tr0 SDO, 10/90% points (measurement circuit A)
tr1
OUTx, VDD = 5 V,10/90% points (measurement circuit B)
tf0 SDO, 10/90% points (measurement circuit A)
tf1
OUTx, VDD = 5 V,10/90% points (measurement circuit B)
tpd0 CLKto SDO↑↓ (measurement circuit A)
tpd1 ¯O¯¯E¯to OUTx↑↓ (measurement circuit B)
– 16 ns
10 30 ns
– 16 ns
10 30 ns
– 30 ns
– 60 ns
tpd2 LEto OUTx↑↓ (measurement circuit B)
– – 60
Output Enable Pulse Duration
tw(OE) (see Timing Diagrams section)
60 –
1Tested at 25°C. Specifications are assured by design and characterization over the operating temperature range of –40°C to 85°C.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
ns
ns
Parameter Measurement Circuits
A6282
SDO
15 pF
A6282
VL
RL
OUTx
CL
(A) Circuit for tf0, tpd0 , and tr0
(B) Circuit for tf1 , tpd1 , tpd2 , and tr1 .
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6

6 Page



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共有リンク

Link :


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