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A6281 の電気的特性と機能

A6281のメーカーはAllegro MicroSystemsです、この部品の機能は「3-Channel Constant Current LED Driver」です。


製品の詳細 ( Datasheet PDF )

部品番号 A6281
部品説明 3-Channel Constant Current LED Driver
メーカ Allegro MicroSystems
ロゴ Allegro MicroSystems ロゴ 




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A6281 Datasheet, A6281 PDF,ピン配置, 機能
A6281
3-Channel Constant Current LED Driver
with Programmable PWM Control
Features and Benefits
3 × 10-bit PWM brightness settings
3 × 7-bit dot correction current settings
5 to 17 V operation
Wide output current range, 10 to 150 mA per channel
Internally generated PWM clock
Serial port operates at up to 5 MHz
Data and clock logic architecture allows single
www.DataSheet4Um.ciocmrocontroller control of large quantities of serially-
connected A6281s at fast data transfer rate
Buffered logic outputs to drive cables
Thermal shutdown and UVLO protection
Power-On Reset
Package: 16-terminal QFN (suffix ES)
3 mm x 3 mm footprint
Description
The A6281 is a 3-channel constant current LED driver that
has a wide range of output currents. The A6281 controls LED
brightness with a Pulse Width Modulation (PWM) scheme
that gives the application the capability of displaying a billion
colors in an RGB cluster. The maximum current is set by an
external resistor.
The LED brightness is controlled by performing PWM control
on the outputs. The brightness data of the PWM signal for
each LED is stored in three 10-bit registers. The peak value
for each LED can be adjusted (dot-corrected) to compensate
for mismatch, aging, and temperature effects. All the internal
latched registers are loaded by a 32-bit shift register. One
address bit controls whether dot correction/clock divider ratio
or brightness data is loaded into the registers. The remaining
bits are used for the data.
TheA6281 is designed to minimize the number of components
needed to drive LEDs with large pixel spacing. A large number
of A6281s can be daisy chained together and controlled by
just four control signals (clock, serial data, latch, and output
enable). Each of these inputs is buffered to drive the next chip
in the chain. Also, VIN can be tied to the LED voltage supply
Continued on the next page…
Power Supply Bus
Clock
Data
Latch
Output Enable
Microprocessor
Control Board
Cat5 UTP
Application Diagram
VLED
VIN OutR OutG OutB
Clock In
Clock Out
Data In
Data Out
Latch In
Latch Out
OE In
OE Out
VREG A6281 REXT
Pixel Board #1
Cat5 UTP
VLED
VIN OutR OutG OutB
Clock In
Clock Out
Data In
Data Out
Latch In
Latch Out
OE In
OE Out
VREG A6281 REXT
Pixel Board #2
Cat5 UTP
Pixel Board #N
Figure 1. Functional drawing of daisy chained display application. Additional pixel boards
with A6281 ICs can be applied.
A6281-DS, Rev. 1

1 Page





A6281 pdf, ピン配列
A6281
3-Channel Constant Current LED Driver
with Programmable PWM Control
www.DataSheet4U.com
Functional Block Diagram
SDI
CI
To PWM Counters
LI
Shift Register
100 ns
One-Shot
REXT
OEI
REXT
VIN
VREG
800 kHz Clock
To PWM Counters
Regulator
Current
Regulator 0
To logic
OUT0
Latched Registers
Current
Regulator 1
OUT1
Current
Regulator 2
OUT2
Pin-out Drawings
SDO
CO
LO
OEO
PGND LGND
REXT
VREG
LGND
VIN
1
2
3
4
PAD
12 OUT0
11 OUT1
10 PGND
9 OUT2
Terminal List Table
Number
1
Name
REXT
Description
An external resistor at this terminal establishes maximum output current
2 VREG Regulator decoupling
3 LGND Logic ground
4 VIN Chip power supply voltage; connect to VREG externally if 4.75 V < VIN < 5.5 V
5 CI Serial clock input; PWM clock if external clock is selected
6 OEI Output enable input; when low (active), the output drivers are enabled; when high (inactive), all
output drivers are turned off (blanked)
7 LI Latch input terminal; serial data is latched with high-level input
8 SDI Serial data input to shift register
9 OUT2 Sinking output terminal
10 PGND Power ground
11 OUT1 Sinking output terminal
12 OUT0 Sinking output terminal
13 SDO Buffered serial data output after shift register
14 LO Buffered latch output
15 OEO Buffered output enable output
16 CO Buffered clock output
PAD
Exposed thermal pad, not internally connected; connect externally to LGND and PGND.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3


3Pages


A6281 電子部品, 半導体
A6281
3-Channel Constant Current LED Driver
with Programmable PWM Control
Functional Description
Shift Register
The A6281 has a 32-bit shift register that loads data through the
SDI (serial data in) pin. The shift register operates by a first-in
first-out (FIFO) method. The most significant bit (MSB, bit 31)
is the first bit shifted in and the least significant bit (LSB, bit 0)
is shifted in last. The serial data is clocked by a rising edge of the
CI (clock in) pin. The SDO (serial data out) pin is updated to the
www.DatasSthaeteeto4fUb.ciotm31 on the falling edge of the CI pin. This will prevent
any race conditions and erroneous data that might occur while
propagating information through multiple A6281s that are daisy
chained together. The contents of the shift register will continue
to propagate on every rising edge of the CI pin. The information
in the shift register is latched on a low-to-high transition of the LI
(Latch In) pin. The LI pin must be brought low before the rising
edge of the next clock pulse, to avoid latching erroneous data.
The latched data remains latched on a rising signal on the OEI
(output enable in) pin.
Output Buffers
The A6281 is designed to allow daisy chaining many A6281s
together. It can pass the clock, data, latch, and output enable
signals from one A6821 to the next without any loss of data due
to duty cycle skewing or signal degradation.
The A6821 is equipped with output buffers that allow the data
signals to travel over long distances through strings of A6281s
without the need for extra driving hardware. The A6281 drives
these signals to TTL levels. Each of the A6281 inputs has a cor-
responding buffered output:
• CI (clock in) pin to CO (clock out) pin
• LI (latch in) pin to LO (latch out) pin
• OEI (output enable in) pin to OEO (output enable out) pin
• SDI (serial data in) pin to SDO (serial data out) pin
The CO (clock out) pin is driven by an internal one-shot circuit.
When the CI pin detects an edge rising through the input thresh-
old, the one-shot circuitry drives the CO pin high for 100 ns. The
CI pin input threshold has hysteresis to prevent false triggering
of the CO signal. The implementation of the one-shot solution
allows many A6281s to be daisy chained together with a consis-
tent clock signal throughout the entire chain without degradation
or loss of synchronicity to the data line.
PWM Brightness Control
The A6281 controls the intensity of each LED by pulse width
modulating the current of each output. The A6281 has three
10-bit brightness registers, one for each output. These brightness
registers set the PWM count value at which the outputs switch
off during each PWM cycle. Each 10-bit brightness register gives
1023 levels of light intensity. The duty cycle, DC, can be deter-
mined by the following equation:
DC = [(PWMn+ 1) / 1024] ×100 (%) ,
where PWMn is the PWM value greater than zero that is stored in
the brightness register.
REXT
SDI
CI
LI
OEI
REXT
VIN
VREG
Shift Register
0 to 6 7 to 8
9
10 to 16 17 to 19 20 to 26 27 28 to 29 30
100 ns
One-Shot
31
Latched Registers
Current Clock
Scalar 0 Mode Unused
7 Bits 2 Bits 1 Bit
800 kHz
PWM Counter 0
10 Bits
Current
Scalar 1
7 Bits
Unused
3 Bits
PWM Counter 1
10 Bits
Current
Test
Scalar 2 Unused Bits
7 Bits 1 Bit ‘’00”
PWM Counter 2
10 Bits
Address
Bit Unused
“1” 1 Bit
Address
Bit Unused
“0” 1 Bit
Current
Regulator 0
+5V
Regulator
Current
Regulator 1
Current
Regulator 2
SDO
CO
LO
OEO
OUT0
Figure 4. Functional Diagram
OUT1
OUT2
PGND LGND
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6

6 Page



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共有リンク

Link :


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