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9693SCC の電気的特性と機能

9693SCCのメーカーはSPTです、この部品の機能は「 SPT9693SCC」です。


製品の詳細 ( Datasheet PDF )

部品番号 9693SCC
部品説明 SPT9693SCC
メーカ SPT
ロゴ SPT ロゴ 




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9693SCC Datasheet, 9693SCC PDF,ピン配置, 機能
FEATURES
• Common mode range –3.0 to +8.0 V
• Low input bias current <100 pA
• Propagation delay 1.5 ns (max)
• Low offset ±25 mV
• Low feedthrough and crosstalk
www.DataSheetD4Uif.fceormential latch control
SPT9693
WIDE INPUT VOLTAGE, JFET COMPARATOR
TECHNICAL DATA
APPLICATIONS
• Automated test equipment
• High-speed instrumentation
• Window comparators
• High-speed timing
• Line receivers
• High-speed triggers
• Threshold detection
• Peak detection
MARCH 1, 2001
GENERAL DESCRIPTION
The SPT9693 is a high-speed, wide common mode volt-
age, JFET input, dual comparator. It is designed for appli-
cations that measure critical timing parameters in which
wide common mode input voltages of –3.0 to +8.0 V are
required. Propagation delays are constant for overdrives
greater than 50 mV.
JFET inputs reduce the input bias currents to the
nanoamp level, eliminating the need for input drivers and
buffers in most applications. The device has differential
analog inputs and complementary logic outputs com-
patible with ECL systems. Each comparator has a
complementary latch enable control that can be driven by
standard ECL logic.
The SPT9693 is available in 20-contact LCC and 20-lead
PLCC packages over the commercial temperature range.
It is also available in die form.
BLOCK DIAGRAM
QA QA QB QB GNDB
GNDA
LEA
LEA
N/C
AVEE(A)
LEB
LEB
N/C
AVEE(B)
AVCC(B)
AVCC(A) –INA +INA +INB –INB
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: 719-528-2300 Fax: 719-528-2370 Web Site: http://www.spt.com e-mail: [email protected]

1 Page





9693SCC pdf, ピン配列
ELECTRICAL SPECIFICATIONS
TA = +25 °C, AVCC = +10 V, AVEE = –10.0 V, RL = 50 Ohm to –2 V, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
AC ELECTRICAL PARAMETERS
Propagation Delay1
50 mV O.D., Slew 10 V/ns
Propagation Delay Tempco
Propagation Delay Skew (A vs B)
Delay Dispersion from
Input Direction
Delay Dispersion from
Input Common Mode
Latch Set-up Time
Latch to Output Delay
50 mV O.D.
www.DataSheLeat4tcUh.cPomulse Width
Latch Hold Time
Rise Time
20% to 80%
Fall Time
20% to 80%
Slew Rate
1Valid for both high-to-low and low-to-high transitions
IV
V
V
V
V
V
V
V
V
V
V
V
MIN
.75
TYP
1.25
2
100
50
60
500
500
500
0
0.45
0.45
5
MAX
1.50
UNITS
ns
ps/ °C
ps
ps
ps
ps
ps
ps
ps
ns
ns
V/ns
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA = +25 °C, and sample tested at the
specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characteri-
zation data.
Parameter is a typical value for information purposes only.
100% production tested at TA = +25 °C. Parameter is guaranteed
over specified temperature range.
SPT
3
SPT9693
3/1/01


3Pages


9693SCC 電子部品, 半導体
GENERAL INFORMATION
The SPT9693 is an ultrahigh-speed dual voltage com-
parator. It offers tight absolute characteristics. The device
has differential analog inputs and complementary logic
outputs compatible with ECL systems. The output stage is
adequate for driving terminated 50 ohm transmission
lines.
Single-channel operation can be accomplished by floating
all pins (including the ground and supply pins) of the un-
used comparator. Power dissipation during single-channel
operation is 50% of the dissipation during dual-channel
operation.
This comparator offers the following improvements over
existing devices:
The SPT9693 has a complementary latch enable control
for each comparator. Both should be driven by standard
ECL logic levels.
A common mode voltage range of –3 V to +8 V is achieved
by a proprietary JFET input design, which requires a
separate negative power supply (AVEE).
www.DataSheTeht4eU.dcoumal comparators have separate AVCC, AVEE, and
grounds for each comparator to achieve high crosstalk
rejection.
Ultra low input bias current and input current offset
Common mode voltage of 3 to +8 V
Short propagation delays
Excellent input and output rejection between
comparator channels
Improved input protection reliability due to JFET input
stage design
All of these combined features produce high-performance
products with timing stability and repeatability for large
system precision.
Figure 1 – Internal Function Diagram
+IN +
PRE
AMP
LATCH
ECL
OUT
–IN –
REF
1
CLK
BUF
REF
2
AVEE VCC GND
LE LE
Q
Q
SPT
6
SPT9693
3/1/01

6 Page



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