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PDF 74V2T126 Data sheet ( Hoja de datos )
| Número de pieza | 74V2T126 | |
| Descripción | DUAL BUS BUFFER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74V2T126
DUAL BUS BUFFER (3-STATE)
s HIGH SPEED: tPD = 3.8ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
www.DataSheet4U.csomICCOC M=P1AµTAI(BMLAEXW.)IaTtHTATT=L2O5°UCTPUTS:
VIH = 2V (MIN), VIL = 0.8V (MAX)
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 4.5V to 5.5V
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74V2T126 is an advanced high-speed CMOS
DUAL BUS BUFFER fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology.
3-STATE control input nG has to be set LOW to
place the output into the high impedance state.
SOT23-8L
ORDER CODES
PACKAGE
SOT23-8L
T&R
74V2T126STR
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 3V to 5V systems
and it is ideal for portable applications like
personal digital assistant, camcorder and all
battery-powered equipment.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 2003
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1 page  
WAVEFORM 1 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
74V2T126
www.DataSheet4U.com
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
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5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74V2T126.PDF ] | |
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| Número de pieza | Descripción | Fabricantes |
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