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PDF U631H64 Data sheet ( Hoja de datos )
| Número de pieza | U631H64 | |
| Descripción | SoftStore 8K x 8 nvSRAM | |
| Fabricantes | Simtek Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de U631H64 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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Obsolete - Not Recommended for New Designs
U631H64
SoftStore 8K x 8 nvSRAM
Features
• High-performance CMOS non-
volatile static RAM 8192 x 8 bits
• 25, 35 and 45 ns Access Times
• 12, 20 and 25 ns Output Enable
Access Times
• Software STORE Initiation
(STORE Cycle Time < 10 ms)
• Automatic STORE Timing
• 105 STORE cycles to EEPROM
•www.DataSheet4U.1c0omyears data retention in
EEPROM
• Automatic RECALL on Power Up
• Software RECALL Initiation
(RECALL Cycle Time < 20 μs)
• Unlimited RECALL cycles from
EEPROM
• Unlimited Read and Write to
SRAM
• Single 5 V ± 10 % Operation
• Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
• QS 9000 Quality Standard
• ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code
Numbers)
• RoHS compliance and Pb- free
• Packages: PDIP28 (300 mil)
SOP28 (330 mil)
Description
The U631H64 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U631H64 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through software sequences.
The U631H64 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
Pin Description
n.c.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 PDIP 22
8 SOP 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
W
n.c.
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
Signal Name
A0 - A12
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
March 31, 2006
STK Control #ML0045
1
Rev 1.0
1 page  
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f
U631H64
Ai
DQi
Output
tcR (1)
Address Valid
ta(A) (2)
Previous Data Valid
tv(A) (9)
Output Data Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
www.DataSheet4U.com
Ai
E
G
DQi
Output
ICC
tcR (1)
Address Valid
ta(A) (2)
ta(E) (3)
ten(E) (7)
ta(G) (4)
ten(G) (8)
High Impedance
ACTIVE
tPU (10)
STANDBY
tPD (11)
tdis(E) (5)
tdis(G) (6)
Output Data Valid
No.
Switching Characteristics
Write Cycle
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
Symbol
25 35 45
Unit
Alt. #1 Alt. #2 IEC Min. Max. Min. Max. Min. Max.
tAVAV tAVAV tcW 25 35 45
tWLWH
tw(W) 20 30 35
tWLEH tsu(W) 20 30 35
tAVWL tAVEL tsu(A)
0
0
0
tAVWH tAVEH tsu(A-WH) 20 30 35
tELWH
tsu(E) 20 30 35
tELEH tw(E) 20 30 35
tDVWH tDVEH tsu(D) 12 18 20
tWHDX tEHDX th(D)
0
0
0
tWHAX tEHAX th(A)
0
0
0
tWLQZ
tdis(W) 10 13 15
tWHQX
ten(W) 5 5 5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
March 31, 2006
STK Control #ML0045
5
Rev 1.0
5 Page 
U631H64
Due to this automatic RECALL, SRAM operation
cannot commence until tRESTORE after VCC exceeds
VSWITCH.
If the U631H64 is in a WRITE state at the end of power
up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 KΩ resistor should be
connected between W and VCC.
Hardware Protection
The U631H64 offers hardware protection against inad-
vertent STORE operation through VCC sense.
For VCC < VSWITCH the software initiated STORE opera-
tion will be inhibited.
www.DataSheet4U.com
Low Average Active Power
The U631H64 has been designed to draw significantly
less power when E is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the VCC level
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
March 31, 2006
STK Control #ML0045
11
Rev 1.0
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet U631H64.PDF ] | |
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