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5C6408-20 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 5C6408-20
部品説明 MT5C6408
メーカ Austin Semiconductor
ロゴ Austin Semiconductor ロゴ 



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5C6408-20 Datasheet, 5C6408-20 PDF,ピン配置, 機能
Austin Semiconductor, Inc.
SRAM
MT5C6408
8K x 8 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-38294
• MIL-STD-883
www.DataSheeFt4EU.cAoTmURES
• High Speed: 12, 15, 20, 25, 35, 45, 55, and 70ns
• Battery Backup: 2V data retention
• High-performance, low-power CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE1\ and CE2
• All inputs and outputs are TTL compatible
OPTIONS
• Timing
12ns access
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
MARKING
-12
-15
-20
-25
-35
-45
-55*
-70*
• Package(s)
Ceramic DIP (300 mil)
Ceramic LCC
Ceramic Flatpack
C No. 108
EC No. 204
F No. 302
• Operating Temperature Ranges
Industrial (-40oC to +85oC)
IT
Military (-55oC to +125oC)
XT
• 2V data retention/low power L
*Electrical characteristics identical to those provided for the
45ns access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
PIN ASSIGNMENT
(Top View)
28-Pin DIP (C)
(300 MIL)
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 Vcc
27 WE\
26 CE2
25 A8
24 A9
23 A11
22 OE\
21 A10
20 CE1\
19 DQ8
18 DQ7
17 DQ6
16 DQ5
15 DQ4
28-Pin LCC (EC)
4 3 2 1 28 27 26
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
DQ0 1 1
25 A8
24 A9
23 A11
2 2 OE\
21 A10
2 0 CE1\
1 9 DQ7
12 13 14 15 16 17 18
28-Pin Flat Pack (F)
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
Vcc
WE\
CE2
A8
A9
A11
OE\
A10
CE1\
DQ8
DQ7
DQ6
DQ5
DQ4
GENERAL DESCRIPTION
The MT5C6408, 8K x 8 SRAM, employs high-speed,
low-power CMOS technology, eliminating the need for clocks
or refreshing. These SRAM’s have equal access and cycle
times.
For flexibility in high-speed memory applications,
Austin Semiconductor offers dual chip enables (CE1\, CE2) and
output enable (OE\) capability. These enhancements can place
the outputs in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH.
Reading is accomplished when WE\ and CE2 remain HIGH and
CE1\ and OE\ go LOW. The device offers a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
These devices operate from a single +5V power sup-
ply and all inputs and outputs are fully TTL compatible.
MT5C6408
Rev. 3.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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