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PDF ADC08500 Data sheet ( Hoja de datos )
| Número de pieza | ADC08500 | |
| Descripción | 500 MSPS A/D Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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June 2007
ADC08500
High Performance, Low Power 8-Bit, 500 MSPS A/D
Converter
General Description
The ADC08500 is a low power, high performance CMOS
analog-to-digital converter that digitizes signals to 8 bits res-
olution at sampling rates up to 500 MSPS. Consuming a
typical 0.8 Watts at 500 MSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
www.DataSheeftu4lUl o.cpoemrating temperature range. The unique folding and in-
terpolating architecture, the fully differential comparator de-
sign, the innovative design of the internal sample-and-hold
amplifier and the self-calibration scheme enable a very flat
response of all dynamic parameters beyond Nyquist, produc-
ing a high 7.5 ENOB with a 250 MHz input signal and a 500
MHz sample rate while providing a 10-18 B.E.R. Output for-
matting is offset binary and the LVDS digital outputs are
compatible with IEEE 1596.3-1996, with the exception of an
adjustable common mode voltage between 0.8V and 1.2V.
The converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40°C ≤ TA ≤ +85°C) temperature range.
Features
■ Internal Sample-and-Hold
■ Single +1.9V ±0.1V Operation
■ Choice of SDR or DDR output clocking
■ Multiple ADC Synchronization Capability
■ Guaranteed No Missing Codes
■ Serial Interface for Extended Control
■ Fine Adjustment of Input Full-Scale Range and Offset
■ Duty Cycle Corrected Sample Clock
Key Specifications
■ Resolution
■ Max Conversion Rate
■ Bit Error Rate
■ ENOB @ 250 MHz Input
■ DNL
■ Power Consumption
■ — Operating
— Power Down Mode
8 Bits
500 MSPS (min)
10-18 (typ)
7.5 Bits (typ)
±0.15 LSB (typ)
0.8 W (typ)
3.5 mW (typ)
Applications
■ Direct RF Down Conversion
■ Digital Oscilloscopes
■ Satellite Set-top boxes
■ Communications Systems
■ Test Instrumentation
Block Diagram
© 2007 National Semiconductor Corporation 202064
20206453
www.national.com
1 page  
Pin Functions
Pin No.
Symbol
32 REXT
34 Tdiode_P
35 Tdiode_N
www.DataSh8e3et4U.com
84
85
86
89
90
91
92
93
94
95
96
100
101
102
103
104
105
106
107
111
112
113
114
115
116
117
118
122
123
124
125
D7-
D7+
D6-
D6+
D5-
D5+
D4-
D4+
D3-
D3+
D2-
D2+
D1-
D1+
D0-
D0+
Dd7-
Dd7+
Dd6-
Dd6+
Dd5-
Dd5+
Dd4-
Dd4+
Dd3-
Dd3+
Dd2-
Dd2+
Dd1-
Dd1+
Dd0-
Dd0+
Equivalent Circuit
Description
External bias resistor connection.
Nominal value is 3.3 kOhms (±0.1%) to ground. See 1.1.1
Self-Calibration.
Temperature Diode Positive (Anode) and Negative (Cathode)
for die temperature measurements. See 2.6.2 Thermal
Management.
Input channel LVDS Data Outputs that are not delayed in the
output demultiplexer. Compared with the Dd outputs, these
outputs represent the later time samples. These outputs
should always be terminated with a 100Ω differential resistor.
Input channel LVDS Data Outputs that are delayed by one
CLK cycle in the output demultiplexer. Compared with the D
outputs, these outputs represent the earlier time sample.
These outputs should always be terminated with a 100Ω
differential resistor.
5 www.national.com
5 Page 
20206404
Note 7: To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,
achieving rated performance requires that the backside exposed pad be well grounded.
Note 8: Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
Level).
Note 9: Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,
therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Transfer Characteristic Figure 2. For relationship between Gain Error and Full-
Scale Error, see Specification Definitions for Gain Error.
www.DataNgSroohtueene1dt04a:rUTeh.icseooalmantaeldogfroamndthcelocdkieincpauptaccaitpaanccietasnbcyesleaardeadnied
capacitances only. Additional
bond wire inductances.
package
capacitances
of
0.65
pF
differential
and
0.95
pF
each
pin
to
Note 11: This parameter is guaranteed by design and is not tested in production.
Note 12: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 13: The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die
capacitances by lead and bond wire inductances.
Note 14: The ADC08500 has two LVDS output buses, which each clock data out at one half the sample rate. The data at each bus is clocked out at one half the
sample rate. The second bus (D0 through D7) has a pipeline latency that is one clock cycle less than the latency of the first bus (Dd0 through Dd7)
Note 15: Tying VBG to the supply rail will increase the output offset voltage (VOS) by 400 mv (typical), as shown in the VOS specification above. Tying VBG to the
supply rail will also affect the differential LVDS output voltage (VOD), causing it to increase by 40mV (typical).
11 www.national.com
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| PDF Descargar | [ Datasheet ADC08500.PDF ] | |
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