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C8051F067 の電気的特性と機能

C8051F067のメーカーはSilicon Laboratoriesです、この部品の機能は「(C8051F060 - C8051F067) Mixed Signal ISP Flash MCU Family」です。


製品の詳細 ( Datasheet PDF )

部品番号 C8051F067
部品説明 (C8051F060 - C8051F067) Mixed Signal ISP Flash MCU Family
メーカ Silicon Laboratories
ロゴ Silicon Laboratories ロゴ 




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C8051F067 Datasheet, C8051F067 PDF,ピン配置, 機能
C8051F060/1/2/3/4/5/6/7
Mixed Signal ISP Flash MCU Family
Analog Peripherals
- Two 16-Bit SAR ADCs
16-bit resolution
±0.75 LSB INL, guaranteed no missing codes
Programmable throughput up to 1 Msps
Operate as two single-ended or one differential con-
verter
Direct memory access; data stored in RAM without
software overhead
Data-dependent windowed interrupt generator
- 10-bit SAR ADC (C8051F060/1/2/3)
Programmable throughput up to 200 ksps
www.DataSheet4U.com 8 external inputs, single-ended or differential
Built-in temperature sensor
- Two 12-bit DACs (C8051F060/1/2/3)
Can synchronize outputs to timers for jitter-free wave-
form generation
- Three Analog Comparators
Programmable hysteresis/response time
- Voltage Reference
- Precision VDD Monitor/Brown-Out Detector
On-Chip JTAG Debug & Boundary Scan
- On-chip debug circuitry facilitates full-speed, non-
intrusive in-circuit/in-system debugging
- Provides breakpoints, single-stepping, watchpoints,
stack monitor; inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- IEEE1149.1 compliant boundary scan
- Complete development kit
High Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instruction set in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Flexible Interrupt sources
Memory
- 4352 Bytes internal data RAM (4 k + 256)
- 64 kB (C8051F060/1/2/3/4/5), 32 kB (C8051F066/7)
Flash; In-system programmable in 512-byte sectors
- External 64 kB data memory interface with multi-
plexed and non-multiplexed modes (C8051F060/2/
4/6)
Digital Peripherals
- 59 general purpose I/O pins (C8051F060/2/4/6)
- 24 general purpose I/O pins (C8051F061/3/5/7)
- Bosch Controller Area Network (CAN 2.0B -
C8051F060/1/2/3)
- Hardware SMBus™ (I2C™ Compatible), SPI™, and
two UART serial ports available concurrently
- Programmable 16-bit counter/timer array with
6 capture/compare modules
- 5 general purpose 16-bit counter/timers
- Dedicated watchdog timer; bi-directional reset pin
Clock Sources
- Internal calibrated precision oscillator: 24.5 MHz
- External oscillator: Crystal, RC, C, or clock
Supply Voltage .......................... 2.7 to 3.6 V
- Multiple power saving sleep and shutdown modes
100-Pin and 64-Pin TQFP Packages Available
Temperature Range: -40 to +85 °C
ANALOGPERIPHERALS
16-bit
1 Msps
ADC
16-bit
1 Msps
ADC
DMA
Interface
VREF
+ ++
- --
VOLTAGE
COMPARATOR
S
10-bit
200ksps
ADC
TEMP
SENSOR
C8051F060/1/2/3Only
12-Bit
DAC
12-Bit
DAC
DIGITAL I/O
CAN 2.0B
C8051F060/1/2/3
Port 0
Port 1
UART0
UART1
SMBus
SPI Bus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
100 pin Only
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25MIPS)
22
INTERRUPTS
64/32 kB
ISP FLASH
DEBUG
CIRCUITRY
4352 B
SRAM
JTAG
CLOCK
SANITY
CIRCUIT CONTROL
Preliminary Rev. 1.2 7/04
Copyright © 2004 by Silicon Laboratories
C8051F060/1/2/3/4/5/6/7
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

1 Page





C8051F067 pdf, ピン配列
C8051F060/1/2/3/4/5/6/7
Table of Contents
1. System Overview.................................................................................................... 19
1.1. CIP-51™ Microcontroller Core.......................................................................... 25
1.1.1. Fully 8051 Compatible.............................................................................. 25
1.1.2. Improved Throughput ............................................................................... 25
1.1.3. Additional Features .................................................................................. 26
1.2. On-Chip Memory............................................................................................... 27
1.3. JTAG Debug and Boundary Scan..................................................................... 28
www.DataSheet4U.com 1.4. Programmable Digital I/O and Crossbar ........................................................... 29
1.5. Programmable Counter Array ........................................................................... 30
1.6. Controller Area Network.................................................................................... 31
1.7. Serial Ports ....................................................................................................... 32
1.8. 16-Bit Analog to Digital Converters................................................................... 33
1.9. 10-Bit Analog to Digital Converter..................................................................... 34
1.10.12-bit Digital to Analog Converters................................................................... 35
1.11.Analog Comparators......................................................................................... 36
2. Absolute Maximum Ratings .................................................................................. 37
3. Global DC Electrical Characteristics .................................................................... 38
4. Pinout and Package Definitions............................................................................ 39
5. 16-Bit ADCs (ADC0 and ADC1) ............................................................................. 51
5.1. Single-Ended or Differential Operation ............................................................. 52
5.1.1. Pseudo-Differential Inputs ........................................................................ 52
5.2. Voltage Reference ............................................................................................ 53
5.3. ADC Modes of Operation.................................................................................. 54
5.3.1. Starting a Conversion............................................................................... 54
5.3.2. Tracking Modes........................................................................................ 54
5.3.3. Settling Time Requirements ..................................................................... 56
5.4. Calibration......................................................................................................... 66
5.5. ADC0 Programmable Window Detector ........................................................... 69
6. Direct Memory Access Interface (DMA0) ............................................................. 75
6.1. Writing to the Instruction Buffer......................................................................... 75
6.2. DMA0 Instruction Format .................................................................................. 76
6.3. XRAM Addressing and Setup ........................................................................... 76
6.4. Instruction Execution in Mode 0........................................................................ 77
6.5. Instruction Execution in Mode 1........................................................................ 78
6.6. Interrupt Sources .............................................................................................. 79
6.7. Data Buffer Overflow Warnings and Errors....................................................... 79
7. 10-Bit ADC (ADC2, C8051F060/1/2/3).................................................................... 87
7.1. Analog Multiplexer ............................................................................................ 88
7.2. Modes of Operation .......................................................................................... 89
7.2.1. Starting a Conversion............................................................................... 89
7.2.2. Tracking Modes........................................................................................ 90
7.2.3. Settling Time Requirements ..................................................................... 91
Rev. 1.2
3


3Pages


C8051F067 電子部品, 半導体
C8051F060/1/2/3/4/5/6/7
18.1.5.Configuring Port 1 and 2 pins as Analog Inputs..................................... 207
18.1.6.Crossbar Pin Assignment Example........................................................ 208
18.2.Ports 4 through 7 (C8051F060/2/4/6 only) ..................................................... 219
18.2.1.Configuring Ports which are not Pinned Out .......................................... 219
18.2.2.Configuring the Output Modes of the Port Pins...................................... 219
18.2.3.Configuring Port Pins as Digital Inputs................................................... 219
18.2.4.Weak Pull-ups ........................................................................................ 219
18.2.5.External Memory Interface ..................................................................... 220
19. Controller Area Network (CAN0, C8051F060/1/2/3) ........................................... 225
19.1.Bosch CAN Controller Operation.................................................................... 227
www.DataSheet4U.com 19.2.CAN Registers................................................................................................ 228
19.2.1.CAN Controller Protocol Registers......................................................... 228
19.2.2.Message Object Interface Registers ...................................................... 228
19.2.3.Message Handler Registers................................................................... 228
19.2.4.CIP-51 MCU Special Function Registers ............................................... 229
19.2.5.Using CAN0ADR, CAN0DATH, and CANDATL To Access CAN Registers
229
19.2.6.CAN0ADR Autoincrement Feature ........................................................ 229
20. System Management BUS / I2C BUS (SMBUS0)................................................ 235
20.1.Supporting Documents ................................................................................... 236
20.2.SMBus Protocol.............................................................................................. 236
20.2.1.Arbitration............................................................................................... 237
20.2.2.Clock Low Extension.............................................................................. 237
20.2.3.SCL Low Timeout................................................................................... 237
20.2.4.SCL High (SMBus Free) Timeout .......................................................... 237
20.3.SMBus Transfer Modes.................................................................................. 238
20.3.1.Master Transmitter Mode ....................................................................... 238
20.3.2.Master Receiver Mode ........................................................................... 238
20.3.3.Slave Transmitter Mode ......................................................................... 239
20.3.4.Slave Receiver Mode ............................................................................. 239
20.4.SMBus Special Function Registers ................................................................ 241
20.4.1.Control Register ..................................................................................... 241
20.4.2.Clock Rate Register ............................................................................... 244
20.4.3.Data Register ......................................................................................... 245
20.4.4.Address Register.................................................................................... 245
20.4.5.Status Register....................................................................................... 246
21. Enhanced Serial Peripheral Interface (SPI0)...................................................... 251
21.1.Signal Descriptions......................................................................................... 252
21.1.1.Master Out, Slave In (MOSI).................................................................. 252
21.1.2.Master In, Slave Out (MISO).................................................................. 252
21.1.3.Serial Clock (SCK) ................................................................................. 252
21.1.4.Slave Select (NSS) ................................................................................ 252
21.2.SPI0 Master Mode Operation ......................................................................... 253
21.3.SPI0 Slave Mode Operation ........................................................................... 255
21.4.SPI0 Interrupt Sources ................................................................................... 255
6 Rev. 1.2

6 Page



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部品番号部品説明メーカ
C8051F060

(C8051F060 - C8051F067) Mixed Signal ISP Flash MCU Family

Silicon Laboratories
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