C8051F017 Datasheet PDF - Silicon Laboratories
Part Number | C8051F017 | |
Description | (C8051F010 - C8051F017) Mixed-Signal 32KB ISP FLASH MCU Family | |
Manufacturers | Silicon Laboratories | |
Logo | ||
There is a preview and C8051F017 download ( pdf file ) link at the bottom of this page. Total 30 Pages |
Preview 1 page No Preview Available ! C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Mixed-Signal 32KB ISP FLASH MCU Family
a
ANALOG PERIPHERALS
- SAR ADC
12-Bit (C8051F000/1/2, C8051F005/6/7)
10-bit (C8051F010/1/2, C8051F015/6/7)
±1LSB INL; No Missing Codes
Programmable Throughput up to 100ksps
Up to 8 External Inputs; Programmable as Single-
Ended or Differential
Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
Data Dependent Windowed Interrupt Generator
Built-in Temperature Sensor (± 3°C)
- Two 12-bit DACs
www.DataSheet4U.c-om Two Analog Comparators
Programmable Hysteresis Values
Configurable to Generate Interrupts or Reset
- Voltage Reference
2.4V; 15 ppm/°C
Available on External Pin
- Precision VDD Monitor/Brown-out Detector
ON-CHIP JTAG DEBUG & BOUNDARY SCAN
- On-Chip Debug Circuitry Facilitates Full Speed, Non-
Intrusive In-System Debug (No Emulator Required!)
- Provides Breakpoints, Single Stepping, Watchpoints, Stack
Monitor
- Inspect/Modify Memory and Registers
- Superior Performance to Emulation Systems Using ICE-
Chips, Target Pods, and Sockets
- IEEE1149.1 Compliant Boundary Scan
- Low Cost Development Kit
HIGH SPEED 8051 µC CORE
- Pipelined Instruction Architecture; Executes 70% of
Instruction Set in 1 or 2 System Clocks
- Up to 25MIPS Throughput with 25MHz Clock
- 21 Vectored Interrupt Sources
MEMORY
- 256 Bytes Internal Data RAM (F000/01/02/10/11/12)
- 2304 Bytes Internal Data RAM (F005/06/07/15/16/17)
- 32k Bytes FLASH; In-System Programmable in 512 byte
Sectors
DIGITAL PERIPHERALS
- 4 Byte-Wide Port I/O; All are 5V tolerant
- Hardware SMBusTM (I2CTM Compatible), SPITM, and UART
Serial Ports Available Concurrently
- Programmable 16-bit Counter/Timer Array with Five
Capture/Compare Modules
- Four General Purpose 16-bit Counter/Timers
- Dedicated Watch-Dog Timer
- Bi-directional Reset
CLOCK SOURCES
- Internal Programmable Oscillator: 2-to-16MHz
- External Oscillator: Crystal, RC,C, or Clock
- Can Switch Between Clock Sources on-the-fly; Useful in
Power Saving Modes
SUPPLY VOLTAGE ........................2.7V to 3.6V
- Typical Operating Current: 12.5mA @ 25MHz
- Multiple Power Saving Sleep and Shutdown Modes
64-Pin TQFP, 48-Pin TQFP, 32-Pin LQFP
Temperature Range: –40°C to +85°C
ANALOG PERIPHERALS
TEMP
SENSOR
PGA
SAR
ADC
12-Bit
DAC
12-Bit
DAC
VREF
+
+-
-
VOLTAGE
COMPARATORS
DIGITAL I/O
PCA
SMBus
SPI Bus
UART
Timer 0
Timer 1
Timer 2
Timer 3
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25MIPS)
32KB
ISP FLASH
CLOCK
CIRCUIT
JTAG
DEBUG
CIRCUITRY
256/2304 B
21
SANITY
SRAM INTERRUPTS CONTROL
Rev. 1.7 11/03
Copyright © 2003 by Silicon Laboratories
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 15.4. XBR1: Port I/O CrossBar Register 1 ........................................................................................107
Figure 15.5. XBR2: Port I/O CrossBar Register 2 ........................................................................................108
15.3. General Purpose Port I/O.................................................................................................................109
15.4. Configuring Ports Which are not Pinned Out..................................................................................109
Figure 15.6. P0: Port0 Register .....................................................................................................................109
Figure 15.7. PRT0CF: Port0 Configuration Register ....................................................................................109
Figure 15.8. P1: Port1 Register .....................................................................................................................110
Figure 15.9. PRT1CF: Port1 Configuration Register ....................................................................................110
Figure 15.10. PRT1IF: Port1 Interrupt Flag Register....................................................................................110
Figure 15.11. P2: Port2 Register ...................................................................................................................111
Figure 15.12. PRT2CF: Port2 Configuration Register ..................................................................................111
Figure 15.13. P3: Port3 Register ...................................................................................................................112
Figure 15.14. PRT3CF: Port3 Configuration Register ..................................................................................112
www.DataSheet4U.com Table 15.2. Port I/O DC Electrical Characteristics........................................................................................112
16. SMBus / I2C Bus...............................................................................................................113
Figure 16.1. SMBus Block Diagram .............................................................................................................113
Figure 16.2. Typical SMBus Configuration ..................................................................................................114
16.1. Supporting Documents ....................................................................................................................114
16.2. Operation .........................................................................................................................................115
Figure 16.3. SMBus Transaction...................................................................................................................115
16.3. Arbitration .......................................................................................................................................116
16.4. Clock Low Extension ......................................................................................................................116
16.5. Timeouts ..........................................................................................................................................116
16.6. SMBus Special Function Registers..................................................................................................116
Figure 16.4. SMB0CN: SMBus Control Register ..........................................................................................118
Figure 16.5. SMB0CR: SMBus Clock Rate Register ....................................................................................119
Figure 16.6. SMB0DAT: SMBus Data Register ...........................................................................................120
Figure 16.7. SMB0ADR: SMBus Address Register .....................................................................................120
Figure 16.8. SMB0STA: SMBus Status Register..........................................................................................121
Table 16.1. SMBus Status Codes ..................................................................................................................122
17. SERIAL PERIPHERAL INTERFACE BUS.................................................................123
Figure 17.1. SPI Block Diagram ...................................................................................................................123
Figure 17.2. Typical SPI Interconnection......................................................................................................124
17.1. Signal Descriptions..........................................................................................................................124
17.2. Operation .........................................................................................................................................125
Figure 17.3. Full Duplex Operation...............................................................................................................125
17.3. Serial Clock Timing.........................................................................................................................126
Figure 17.4. Data/Clock Timing Diagram .....................................................................................................126
17.4. SPI Special Function Registers........................................................................................................127
Figure 17.5. SPI0CFG: SPI Configuration Register......................................................................................127
Figure 17.6. SPI0CN: SPI Control Register ..................................................................................................128
Figure 17.7. SPI0CKR: SPI Clock Rate Register..........................................................................................129
Figure 17.8. SPI0DAT: SPI Data Register ....................................................................................................129
18. UART.................................................................................................................................130
Figure 18.1. UART Block Diagram ..............................................................................................................130
18.1. UART Operational Modes...............................................................................................................131
Table 18.1. UART Modes .............................................................................................................................131
Figure 18.2. UART Mode 0 Interconnect......................................................................................................131
Figure 18.3. UART Mode 0 Timing Diagram...............................................................................................131
Figure 18.4. UART Mode 1 Timing Diagram...............................................................................................132
Figure 18.5. UART Modes 1, 2, and 3 Interconnect Diagram ......................................................................133
Figure 18.6. UART Modes 2 and 3 Timing Diagram....................................................................................134
18.2. Multiprocessor Communications .....................................................................................................135
Figure 18.7. UART Multi-Processor Mode Interconnect Diagram ...............................................................135
5 Rev. 1.7
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