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C8051F006 の電気的特性と機能

C8051F006のメーカーはSilicon Laboratoriesです、この部品の機能は「(C8051F000 - C8051F007) Mixed-Signal 32KB ISP FLASH MCU Family」です。


製品の詳細 ( Datasheet PDF )

部品番号 C8051F006
部品説明 (C8051F000 - C8051F007) Mixed-Signal 32KB ISP FLASH MCU Family
メーカ Silicon Laboratories
ロゴ Silicon Laboratories ロゴ 




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C8051F006 Datasheet, C8051F006 PDF,ピン配置, 機能
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Mixed-Signal 32KB ISP FLASH MCU Family
a
ANALOG PERIPHERALS
- SAR ADC
12-Bit (C8051F000/1/2, C8051F005/6/7)
10-bit (C8051F010/1/2, C8051F015/6/7)
±1LSB INL; No Missing Codes
Programmable Throughput up to 100ksps
Up to 8 External Inputs; Programmable as Single-
Ended or Differential
Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
Data Dependent Windowed Interrupt Generator
Built-in Temperature Sensor (± 3°C)
- Two 12-bit DACs
www.DataSheet4U.c-om Two Analog Comparators
Programmable Hysteresis Values
Configurable to Generate Interrupts or Reset
- Voltage Reference
2.4V; 15 ppm/°C
Available on External Pin
- Precision VDD Monitor/Brown-out Detector
ON-CHIP JTAG DEBUG & BOUNDARY SCAN
- On-Chip Debug Circuitry Facilitates Full Speed, Non-
Intrusive In-System Debug (No Emulator Required!)
- Provides Breakpoints, Single Stepping, Watchpoints, Stack
Monitor
- Inspect/Modify Memory and Registers
- Superior Performance to Emulation Systems Using ICE-
Chips, Target Pods, and Sockets
- IEEE1149.1 Compliant Boundary Scan
- Low Cost Development Kit
HIGH SPEED 8051 µC CORE
- Pipelined Instruction Architecture; Executes 70% of
Instruction Set in 1 or 2 System Clocks
- Up to 25MIPS Throughput with 25MHz Clock
- 21 Vectored Interrupt Sources
MEMORY
- 256 Bytes Internal Data RAM (F000/01/02/10/11/12)
- 2304 Bytes Internal Data RAM (F005/06/07/15/16/17)
- 32k Bytes FLASH; In-System Programmable in 512 byte
Sectors
DIGITAL PERIPHERALS
- 4 Byte-Wide Port I/O; All are 5V tolerant
- Hardware SMBusTM (I2CTM Compatible), SPITM, and UART
Serial Ports Available Concurrently
- Programmable 16-bit Counter/Timer Array with Five
Capture/Compare Modules
- Four General Purpose 16-bit Counter/Timers
- Dedicated Watch-Dog Timer
- Bi-directional Reset
CLOCK SOURCES
- Internal Programmable Oscillator: 2-to-16MHz
- External Oscillator: Crystal, RC,C, or Clock
- Can Switch Between Clock Sources on-the-fly; Useful in
Power Saving Modes
SUPPLY VOLTAGE ........................2.7V to 3.6V
- Typical Operating Current: 12.5mA @ 25MHz
- Multiple Power Saving Sleep and Shutdown Modes
64-Pin TQFP, 48-Pin TQFP, 32-Pin LQFP
Temperature Range: –40°C to +85°C
ANALOG PERIPHERALS
TEMP
SENSOR
PGA
SAR
ADC
12-Bit
DAC
12-Bit
DAC
VREF
+
+-
-
VOLTAGE
COMPARATORS
DIGITAL I/O
PCA
SMBus
SPI Bus
UART
Timer 0
Timer 1
Timer 2
Timer 3
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25MIPS)
32KB
ISP FLASH
CLOCK
CIRCUIT
JTAG
DEBUG
CIRCUITRY
256/2304 B
21
SANITY
SRAM INTERRUPTS CONTROL
Rev. 1.7 11/03
Copyright © 2003 by Silicon Laboratories

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C8051F006 pdf, ピン配列
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 5.1. 12-Bit ADC Electrical Characteristics............................................................................................38
Table 5.1. 12-Bit ADC Electrical Characteristics............................................................................................39
6. ADC (10-Bit, C8051F010/1/2/5/6/7 Only).........................................................................40
Figure 6.1. 10-Bit ADC Functional Block Diagram........................................................................................40
6.1. Analog Multiplexer and PGA................................................................................................................40
6.2. ADC Modes of Operation......................................................................................................................41
Figure 6.2. 10-Bit ADC Track and Conversion Example Timing...................................................................41
Figure 6.3. Temperature Sensor Transfer Function.........................................................................................42
Figure 6.4. AMX0CF: AMUX Configuration Register (C8051F01x) ............................................................42
Figure 6.5. AMX0SL: AMUX Channel Select Register (C8051F01x)...........................................................43
Figure 6.6. ADC0CF: ADC Configuration Register (C8051F01x).................................................................44
Figure 6.7. ADC0CN: ADC Control Register (C8051F01x) ..........................................................................45
Figure 6.8. ADC0H: ADC Data Word MSB Register (C8051F01x) .............................................................46
www.DataSheet4U.com Figure 6.9. ADC0L: ADC Data Word LSB Register (C8051F01x)...............................................................46
6.3. ADC Programmable Window Detector.................................................................................................47
Figure 6.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F01x) ..................................47
Figure 6.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F01x) ...................................47
Figure 6.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F01x) .......................................47
Figure 6.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F01x).........................................47
Figure 6.14. 10-Bit ADC Window Interrupt Examples, Right Justified Data.................................................48
Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data ...................................................48
Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data ...................................................49
Table 6.1. 10-Bit ADC Electrical Characteristics............................................................................................49
Table 6.1. 10-Bit ADC Electrical Characteristics............................................................................................50
7. DACs, 12 BIT VOLTAGE MODE....................................................................................51
Figure 7.1. DAC Functional Block Diagram....................................................................................................51
Figure 7.2. DAC0H: DAC0 High Byte Register .............................................................................................52
Figure 7.3. DAC0L: DAC0 Low Byte Register ..............................................................................................52
Figure 7.4. DAC0CN: DAC0 Control Register...............................................................................................52
Figure 7.5. DAC1H: DAC1 High Byte Register .............................................................................................53
Figure 7.6. DAC1L: DAC1 Low Byte Register ..............................................................................................53
Figure 7.7. DAC1CN: DAC1 Control Register...............................................................................................53
Table 7.1. DAC Electrical Characteristics.......................................................................................................54
8. COMPARATORS ..............................................................................................................55
Figure 8.1. Comparator Functional Block Diagram ........................................................................................55
Figure 8.2. Comparator Hysteresis Plot...........................................................................................................56
Figure 8.3. CPT0CN: Comparator 0 Control Register ....................................................................................57
Figure 8.4. CPT1CN: Comparator 1 Control Register ....................................................................................58
Table 8.1. Comparator Electrical Characteristics ............................................................................................59
9. VOLTAGE REFERENCE ................................................................................................60
Figure 9.1. Voltage Reference Functional Block Diagram .............................................................................60
Figure 9.2. REF0CN: Reference Control Register ..........................................................................................61
Table 9.1. Reference Electrical Characteristics ...............................................................................................61
10. CIP-51 CPU.........................................................................................................................62
Figure 10.1. CIP-51 Block Diagram................................................................................................................62
10.1. INSTRUCTION SET.........................................................................................................................63
Table 10.1. CIP-51 Instruction Set Summary..................................................................................................65
10.2. MEMORY ORGANIZATION ..........................................................................................................68
Figure 10.2. Memory Map...............................................................................................................................69
10.3. SPECIAL FUNCTION REGISTERS................................................................................................70
Table 10.2. Special Function Register Memory Map ......................................................................................70
Table 10.3. Special Function Registers ...........................................................................................................70
Figure 10.3. SP: Stack Pointer.........................................................................................................................74
Figure 10.4. DPL: Data Pointer Low Byte ......................................................................................................74
3 Rev. 1.7


3Pages


C8051F006 電子部品, 半導体
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 18.2. Oscillator Frequencies for Standard Baud Rates ........................................................................136
Figure 18.8. SBUF: Serial (UART) Data Buffer Register.............................................................................136
Figure 18.9. SCON: Serial Port Control Register..........................................................................................137
19. TIMERS ............................................................................................................................138
19.1. Timer 0 and Timer 1 ........................................................................................................................138
Figure 19.1. T0 Mode 0 Block Diagram........................................................................................................139
Figure 19.2. T0 Mode 2 Block Diagram........................................................................................................140
Figure 19.3. T0 Mode 3 Block Diagram........................................................................................................141
Figure 19.4. TCON: Timer Control Register.................................................................................................142
Figure 19.5. TMOD: Timer Mode Register...................................................................................................143
Figure 19.6. CKCON: Clock Control Register..............................................................................................144
Figure 19.7. TL0: Timer 0 Low Byte ............................................................................................................145
Figure 19.8. TL1: Timer 1 Low Byte ............................................................................................................145
www.DataSheet4U.com Figure 19.9. TH0: Timer 0 High Byte ...........................................................................................................145
Figure 19.10. TH1: Timer 1 High Byte .........................................................................................................145
19.2. Timer 2 ............................................................................................................................................146
Figure 19.11. T2 Mode 0 Block Diagram......................................................................................................147
Figure 19.12. T2 Mode 1 Block Diagram......................................................................................................148
Figure 19.13. T2 Mode 2 Block Diagram......................................................................................................149
Figure 19.14. T2CON: Timer 2 Control Register..........................................................................................150
Figure 19.15. RCAP2L: Timer 2 Capture Register Low Byte ......................................................................151
Figure 19.16. RCAP2H: Timer 2 Capture Register High Byte .....................................................................151
Figure 19.17. TL2: Timer 2 Low Byte ..........................................................................................................151
Figure 19.18. TH2: Timer 2 High Byte .........................................................................................................151
19.3. Timer 3 ............................................................................................................................................152
Figure 19.19. Timer 3 Block Diagram...........................................................................................................152
Figure 19.20. TMR3CN: Timer 3 Control Register ......................................................................................152
Figure 19.21. TMR3RLL: Timer 3 Reload Register Low Byte ....................................................................153
Figure 19.22. TMR3RLH: Timer 3 Reload Register High Byte ...................................................................153
Figure 19.23. TMR3L: Timer 3 Low Byte ....................................................................................................153
Figure 19.24. TMR3H: Timer 3 High Byte ...................................................................................................153
20. PROGRAMMABLE COUNTER ARRAY....................................................................154
Figure 20.1. PCA Block Diagram .................................................................................................................154
20.1. Capture/Compare Modules ..............................................................................................................155
Table 20.1. PCA0CPM Register Settings for PCA Capture/Compare Modules ...........................................155
Figure 20.2. PCA Interrupt Block Diagram...................................................................................................155
Figure 20.3. PCA Capture Mode Diagram ....................................................................................................156
Figure 20.4. PCA Software Timer Mode Diagram........................................................................................157
Figure 20.5. PCA High Speed Output Mode Diagram..................................................................................157
Figure 20.6. PCA PWM Mode Diagram .......................................................................................................158
20.2. PCA Counter/Timer.........................................................................................................................159
Table 20.2. PCA Timebase Input Options.....................................................................................................159
Figure 20.7. PCA Counter/Timer Block Diagram.........................................................................................159
20.3. Register Descriptions for PCA ........................................................................................................160
Figure 20.8. PCA0CN: PCA Control Register ...............................................................................................160
Figure 20.9. PCA0MD: PCA Mode Register ................................................................................................161
Figure 20.10. PCA0CPMn: PCA Capture/Compare Registers......................................................................162
Figure 20.11. PCA0L: PCA Counter/Timer Low Byte .................................................................................163
Figure 20.12. PCA0H: PCA Counter/Timer High Byte ................................................................................163
Figure 20.13. PCA0CPLn: PCA Capture Module Low Byte ........................................................................163
Figure 20.14. PCA0CPHn: PCA Capture Module High Byte.......................................................................163
21. JTAG (IEEE 1149.1) ........................................................................................................164
Figure 21.1. IR: JTAG Instruction Register ..................................................................................................164
21.1. Boundary Scan.................................................................................................................................165
Rev. 1.7
6

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部品番号部品説明メーカ
C8051F000

(C8051F000 - C8051F007) Mixed-Signal 32KB ISP FLASH MCU Family

Cygnal
Cygnal
C8051F000

(C8051F000 - C8051F007) Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories
Silicon Laboratories
C8051F001

(C8051F000 - C8051F007) Mixed-Signal 32KB ISP FLASH MCU Family

Cygnal
Cygnal
C8051F001

(C8051F000 - C8051F007) Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories
Silicon Laboratories


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