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PDF HV2321 Data sheet ( Hoja de datos )
| Número de pieza | HV2321 | |
| Descripción | Analog Switch | |
| Fabricantes | Supertex | |
| Logotipo |  |
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Supertex inc.
HV2321
Low Charge Injection, 8-Channel, Unipolar,
Negative High Voltage, Analog Switch With Bleed Resistors
Features
►► Low on-resistance, 14Ω max.
►► Integrated bleed resistors on the outputs
►► 3.3 or 5.0V CMOS input logic level
►► 20MHz data shift clock frequency
►► Very low quiescent power dissipation (-10µA)
►► Low parasitic capacitance
►► DC to 50MHz small signal frequency response
►► -60dB typical off-isolation at 5.0MHz
►► CMOS logic circuitry for low power
►► Excellent noise immunity
►► Cascadable serial data register with latches
Applications
►► NDT metal flaw detection
►► Medical ultrasound imaging
►► Piezoelectric transducer drivers
►► Inkjet printer heads
►► Optical MEMS modules
General Description
The Supertex HV2321 is a low charge injection, 8-channel,
unipolar, negative high voltage, analog switch integrated circuit
(IC) with bleed resistors. The device can be used in applications
requiring high voltage switching controlled by low voltage signals,
such as NDT metal flaw detection, medical ultrasound imaging,
piezoelectric transducer drivers, and printers. The bleed resistors
eliminate voltage built up on capacitive loads such as piezoelectric
transducers.
Data is input into an 8-bit shift register and then retained in an 8-bit
latch. To reduce any possible clock feed-through noise, the latch
enable bar should be left high until all bits are clocked in. Data is
clocked in during the rising edge of the clock.
Using HVCMOS technology, this device combines high voltage
bilateral DMOS switches and low power CMOS logic to provide
efficient control of high voltage analog signals.
Block Diagram
Latches
D
LE
CLR
Level
Shifters
Output
Switches
SW0
CLK
8-Bit
Shift
DIN Register
D
LE
CLR
D
LE
CLR
SW1
SW2
DOUT
D
LE
CLR
SW6
D
LE
CLR
SW7
VDD GND LE CLR
VNN VPP
RGND
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
1 page  
HV2321
Truth Table
D0 D1 D2 D3 D4 D5 D6 D7 LE CLR SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
L L L Off
H L L On
L
LL
Off
H
LL
On
L
LL
Off
H
LL
On
L
LL
Off
H
LL
On
L LL
Off
H LL
On
L LL
Off
H LL
On
L LL
Off
H LL
On
LLL
Off
HLL
On
XXXXXXXXH L
Hold Previous State
XXXXXXXXXH
All Switches Off
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L to H transition of the CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch.
4.
5.
SDhOUifTt
is high when data in the
register clocking has no
shift register
effect on the
7 is high.
switch states
if
LE
is
high.
6. The CLR clear input overrides all other inputs.
Logic Timing Waveforms
DN+1
DN
DATA IN
50%
50%
DN-1
LE
CLK
50%
50%
tWLE
tSD
50%
tSU th
tDO
50%
DATA OUT
VOUT OFF
(typ)
ON
50%
tOFF
90%
tON
10%
CLR
50%
50%
tWCL
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet HV2321.PDF ] | |
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