DataSheet.jp

K3N5VU1000F-DC の電気的特性と機能

K3N5VU1000F-DCのメーカーはSamsung Semiconductorです、この部品の機能は「16M-Bit (2Mx8 / 1Mx16) CMOS Mask ROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 K3N5VU1000F-DC
部品説明 16M-Bit (2Mx8 / 1Mx16) CMOS Mask ROM
メーカ Samsung Semiconductor
ロゴ Samsung Semiconductor ロゴ 




このページの下部にプレビューとK3N5VU1000F-DCダウンロード(pdfファイル)リンクがあります。
Total 3 pages

No Preview Available !

K3N5VU1000F-DC Datasheet, K3N5VU1000F-DC PDF,ピン配置, 機能
K3N5V(U)1000F-D(G)C
CMOS MASK ROM
16M-Bit (2Mx8 /1Mx16) CMOS MASK ROM
FEATURES
Switchable organization
2,097,152 x 8(byte mode)
1,048,576 x 16(word mode)
Fast access time
3.3V Operation : 100ns(Max.)@CL=50pF,
120ns(Max.)@CL=100pF
3.0V Operation : 120ns(Max.)@CL=100pF
Supply voltage : single +3.0V/single +3.3V
www.DataSheet4UC.cuormrent consumption
Operating : 40mA(Max.)
Standby : 30µA(Max.)
Fully static operation
All inputs and outputs TTL compatible
Three state outputs
Package
-. K3N5V(U)1000F-DC : 42-DIP-600
-. K3N5V(U)1000F-GC : 44-SOP-600
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The K3N5V(U)1000F-D(G)C is a fully static mask programma-
ble ROM fabricated using silicon gate CMOS process technol-
ogy, and is organized either as 2,097,152 x 8 bit(byte mode) or
as 1,048,576x16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3N5V(U)1000F-DC is packaged in a 42-DIP and the
K3N5V(U)1000F-GC in a 44-SOP.
PIN CONFIGURATION
A19
.
.
.
.
.
.
.
.
A0
A-1
X
BUFFERS
AND
DECODER
Y
BUFFERS
AND
DECODER
MEMORY CELL
MATRIX
(1,048,576x16/
2,097,152x8)
SENSE AMP.
DATA OUT
BUFFERS
...
CE
OE
BHE
]
CONTROL
LOGIC
Q0/Q8
Pin Name
A0 - A19
Q0 - Q14
Q15 /A-1
Pin Function
Address Inputs
Data Outputs
Output 15(Word mode)/
LSB Address(Byte mode)
BHE
CE
OE
VCC
VSS
N.C
Word/Byte selection
Chip Enable
Output Enable
Power
Ground
No Connection
Q7/Q15
A18 1
A17 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
CE 11
VSS 12
OE 13
Q0 14
Q8 15
Q1 16
Q9 17
Q2 18
Q10 19
Q3 20
Q11 21
DIP
42 A19
N.C 1
41 A8
A18 2
40 A9
A17 3
39 A10
A7 4
38 A11
A6 5
37 A12
A5 6
36 A13
A4 7
35 A14
A3 8
34 A15
A2 9
33 A16
A1 10
32 BHE
A0 11
31 VSS CE 12
30 Q15/A-1 VSS 13
29 Q7
OE 14
28 Q14
Q0 15
27 Q6
Q8 16
26 Q13
Q1 17
25 Q5
24 Q12
23 Q4
22 VCC
Q9 18
Q2 19
Q10 20
Q3 21
Q11 22
SOP
44 N.C
43 A19
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BHE
32 VSS
31 Q15/A-1
30 Q7
29 Q14
28 Q6
27 Q13
26 Q5
25 Q12
24 Q4
23 VCC
K3N5V(U)1000F-DC
K3N5V(U)1000F-GC

1 Page





K3N5VU1000F-DC pdf, ピン配列
K3N5V(U)1000F-D(G)C
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=3.3V/3.0V±0.3V, unless otherwise noted.)
TEST CONDITIONS
Item
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
Value
0.45V to 2.4V
10ns
1.5V
1 TTL Gate and CL=50pF or 100pF
www.DataSheet4U.com
READ CYCLE
Item
Symbol
K3N5V1000F-D(G)C10
(CL=50pF)
Min Max
K3N5V1000F-D(G)C12
(CL=100pF)
Min Max
K3N5U1000F-D(G)C12
(CL=100pF)
Min Max
Unit
Read Cycle Time
tRC 100
120
120 ns
Chip Enable Access Time
tACE
100
120
120 ns
Address Access Time
tAA
100
120
120 ns
Output Enable Access Time
tOE
50
60
60 ns
Output or Chip Disable to
Output High-Z
tDF
20
20
20 ns
Output Hold from Address Change tOH
0
0
0 ns
TIMING DIAGRAM
READ
ADD
A0~A19
A-1(*1)
CE
OE
DOUT
D0~D7
D8~D15(*2)
ADD1
tACE
tRC
tOE
ADD2
tAA
VALID DATA
tOH
VALID DATA
tDF(*3)
NOTES :
*1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)
*2. Word Mode only.(BHE = VIH)
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.


3Pages





ページ 合計 : 3 ページ
 
PDF
ダウンロード
[ K3N5VU1000F-DC データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
K3N5VU1000F-DC

16M-Bit (2Mx8 / 1Mx16) CMOS Mask ROM

Samsung Semiconductor
Samsung Semiconductor
K3N5VU1000F-DGC

16M-Bit (2Mx8 / 1Mx16) CMOS Mask ROM

Samsung Semiconductor
Samsung Semiconductor


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap