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UT54ACS191 の電気的特性と機能

UT54ACS191のメーカーはETCです、この部品の機能は「Synchronous 4-Bit Up-Down Binary Counters」です。


製品の詳細 ( Datasheet PDF )

部品番号 UT54ACS191
部品説明 Synchronous 4-Bit Up-Down Binary Counters
メーカ ETC
ロゴ ETC ロゴ 




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UT54ACS191 Datasheet, UT54ACS191 PDF,ピン配置, 機能
UT54ACS191/UT54ACTS191
Radiation-Hardened
Synchronous 4-Bit Up-Down Binary Counters
FEATURES
Single down/up count control line
counters
Fully synchronous in count modes
www.DataSheetA4Usy.cnocmhronously presetable with load control
radiation-hardened CMOS
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
DESCRIPTION
The UT54ACS191 and the UT54ACTS191 are synchronous 4-
bit reversible up-down binary counters. Synchronous counting
operation is provided by having all flip-flops clocked simulta-
neously so that the outputs change coincident with each other
when so instructed. Synchronous operation eliminates the out-
put counting spikes associated with asynchronous counters.
The outputs of the four flip-flops are triggered on a low-to-high-
level transition of the clock input if the enable input (CTEN) is
low. A logic one applied to CTEN inhibits counting. The di-
rection of the count is determined by the level of the down/up
(D/U) input. When D/U is low, the counter counts up and when
D/U is high, it counts down.
The counters feature a fully independent clock circuit. Changes
at control inputs (CTEN and D/U) that will modify the operating
mode have no effect on the contents of the counter until clocking
occurs.
The counters are fully programmable. The outputs may be
preset to either logic level by placing a low on the load input
and entering the desired data at the data inputs. The output will
change to agree with the data inputs independently of the level
of the clock input. The asynchronous load allows counters to
be used as modulo-N dividers by simply modifying the count
length with the preset inputs.
Two outputs have been made available to perform the cascading
function: ripple clock and maximum/minimum (MAX/MIN)
count. The MAX/MIN output produces a high-level output
pulse with a duration approximately equal to one complete cycle
of the clock while the count is zero (all outputs low) counting
down or maximum (15) counting up.
123
PINOUTS
16-Pin DIP
Top View
B1
V
B 15 A
A3
13 RCO
D/ 5
Q6
LOAD
Q 10 C
SS 9
16-Lead Flatpack
Top View
Q
Q
CTEN
U
C
D
SS
16
2
14
4
12
11
7
9
DD
CLK
MAX/MIN
C
The ripple clock output (RCO) produces a low-level output
pulse under those same conditions but only while the clock input
is low. The counters easily cascade by feeding the RCO to the
enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. Use the
MAX/MIN count output to accomplish look-ahead for high-
speed operation.
The devices are characterized over full military temperature
range of -55 C to +125
Rad-Hard MSI Logic

1 Page





UT54ACS191 pdf, ピン配列
UT54ACS191/UT54ACTS191
RADIATION HARDNESS SPECIFICATIONS 1
PARAMETER
Total Dose
SEU Threshold 2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm2/mg
MeV-cm2/mg
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
www.DataSheAeBt4SUO.coLmUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
VDD
VI/O
TSTG
TJ
TLS
JC
II
PD
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to VDD +.3
-65 to +150
+175
+300
20
10
1
UNITS
V
V
C
C
C
C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VDD
VIN
TC
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to VDD
-55 to + 125
UNITS
V
V
C
125 Rad-Hard MSI Logic


3Pages


UT54ACS191 電子部品, 半導体
UT54ACS191/UT54ACTS191
AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C)
SYMBOL
PARAMETER
tPLH LOAD to Qn
tPHL LOAD to Qn
tPLH Data In to Qn
tPHL Data In to Qn
tPLH
www.DataSheet4U.com
tPHL
CLK to Qn
CLK to Qn
tPLH CLK to RCO
tPHL CLK to RCO
tPLH CLK to MAX/MIN
tPHL CLK to MAX/MIN
tPLH D/U to RCO
tPHL D/U to RCO
tPLH D/U to MAX/MIN
tPHL D/U to MAX/MIN
tPLH CTEN to RCO
tPHL CTEN to RCO
fMAX
Maximum clock frequency
tSU1 LOAD , CTEN, D/U
Setup time before CLK
tSU2 A, B, C, D setup time before LOAD
tH1 CTEN and D/U hold time after CLK
tH23 A, B, C, D hold time after LOAD
tW Minimum pulse width
CLK high
CLK low
LOAD low
MINIMUM
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
12
5
2
2
8
MAXIMUM
20
22
23
19
17
22
12
15
22
23
16
18
15
17
12
16
63
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose 1E6 rads(Si).
3. Based on characterization, hold time (tH2) of 0ns can be assumed if data setup time (tSU2) is >10ns. This is guaranteed, but not tested.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
Rad-Hard MSI Logic
128

6 Page



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