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PDF UT54ACS273 Data sheet ( Hoja de datos )
| Número de pieza | UT54ACS273 | |
| Descripción | Octal D-Flip-Flops | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de UT54ACS273 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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UT54ACS273/UT54ACTS273
Radiation-Hardened
Octal D-Flip-Flops with Clear
FEATURES
Contains eight flip-flops with single-rail outputs
Buffered clock and direct clear inputs
Individual data input to each flip-flop
www.DataSheetA4Up.pcloimcations include:
- Buffer/storage registers, shift registers, and pattern
generators
radiation-hardened CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 20-pin DIP
- 20-lead flatpack
DESCRIPTION
The UT54ACS273 and the UT54ACTS273 are positive-edge-
triggered D-type flip-flops with a direct clear input.
Information at the D inputs meeting the setup time requirements
is transferred to the Q outputs on the positive-going edge of the
clock pulse. When the clock input is at either the high or low
level, the D input signal has no effect at the output.
The devices are characterized over full military temperature
range of -55 C to +125 C.
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
CLK
Dx
Qx
LXX
HH
L
H
H LL
H L X No change
PINOUTS
20-Pin DIP
Top View
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
VSS
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
VDD
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
20-Lead Flatpack
Top View
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
VSS
LOGIC SYMBOL
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
VDD
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
(1)
CLR
(11)
CLK
1D (3)
(4)
2D
3D (7)
(8)
4D
5D (13)
(14)
6D
7D (17)
(18)
8D
R
C1
1D
(2)
1Q
(5)
2Q
(6)
3Q
(9)
4Q
(12)
5Q
(15)
(16) 6Q
7Q
(19)
8Q
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984
and IEC Publication 617-12.
189 RadHard MSI Logic
1 page  
UT54ACS273/UT54ACTS273
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
www.DataSheet4U.com
193 RadHard MSI Logic
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet UT54ACS273.PDF ] | |
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