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PDF MX29L3211 Data sheet ( Hoja de datos )
| Número de pieza | MX29L3211 | |
| Descripción | CMOS SINGLE VOLTAGE PAGEMODE FLASH EEPROM | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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ADVANCED INFORMATION
MX29L3211
32M-BIT [4M x 8/2M x 16] CMOS
SINGLE VOLTAGE PAGEMODE FLASH EEPROM
FEATURES
• 3.3V ± 10% write, erase and read
• Endurance: 10,000 cycles
• Fast random access time: 100ns/120ns
• Fast pagemode access time: 50ns
www.DataSheet•4UP.caogme access depth: 16 bytes/8 words
• Sector erase architecture
- 32 equal sectors of 64K word each
- Sector erase time: 200ms typical
• Auto Erase and Auto Program Algorithms
- Automatically erases any one of the sectors or the
whole chip with Erase Suspend capability
- Automatically programs and verifies data at specified
addresses
• Status Register feature for detection of program or
erase cycle completion
• Low VCC write inhibit is equal to or less than 1.8V
• Software data protection
• Page program operation
- Internal address and data latches for 256 bytes/128
words per page
- Page programming time: 5ms typical
• Low power dissipation
- 50mA active current
- 20uA standby current
• Two independently Protected sectors
• Industry standard surface mount packaging
- 44 pin SOP (500mil)
- 48 TSOP(I)
GENERAL DESCRIPTION
The MX29L3211 is a 32-mega bit pagemode Flash
memory organized as either 4M word x 8 or 2M byte x 16.
The MX29L3211 includes 32 sectors of 64K words.
MXIC's Flash memories offer the most cost-effective
and reliable read/write non-volatile random access
memory and fast page mode access. The MX29L3211
is packaged 44-pin SOP and 48-pin TSOP. It is designed
to be reprogrammed and erased in-system or in-standard
EPROM programmers.
The standard MX29L3211 offers access times as fast as
100ns,allowing operation of high-speed microprocessors
without wait. To eliminate bus contention, the MX29L3211
has separate chip enable CE, output enable (OE), and
write enable (WE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29L3211 uses a command register to manage this
functionality.
To allow for simple in-system reprogrammability, the
MX29L3211 does not require high input voltages for
programming. Three-volt-only commands determine
the operation of the device. Reading data out of the
device is similar to reading from an EPROM.
MXIC Flash technology reliably stores memory contents
even after 10,000 cycles. The MXIC's cell is designed
to optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide
processing and low internal electric fields for erase and
programming operations produces reliable cycling. The
MX29L3211 uses a 3.3V ± 10% VCC supply to perform
the Auto Erase and Auto Program algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC +1V.
P/N:PM0641
REV. 0.3, NOV. 06, 2001
1
1 page  
MX29L3211
BUS OPERATION
Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
Table 2.1 Bus Operations for Word-Wide Mode (BYTE = VIH)
Mode
Read
www.DataSheet4U.com
Output Disable
Standby
Manufacturer ID
Device ID
Write
Notes
1
1
1
2,4
2,4
1,3
CE
VIL
VIL
VIH
VIL
VIL
VIL
OE WE A0 A1
VIL VIH X X
VIH VIH X X
X XXX
VIL VIH VIL VIL
VIL VIH VIH VIL
VIH VIL X X
A9
X
X
X
VID
VID
X
Q0-Q7
DOUT
High Z
High Z
C2H
F9H
DIN
Q8-Q14
DOUT
High Z
HIgh Z
00H
00H
DIN
Q15/A-1
DOUT
HighZ
HighZ
0B
0B
DIN
Table2.2 Bus Operations for BYTE-Wide Mode (BYTE = VIL)
Mode
Read
Output Disable
Standby
Manufacturer ID
Device ID
Write
Notes CE
1 VIL
1 VIL
1 VIH
2,4 VIL
2,4 VIL
1,3 VIL
OE WE A0 A1 A9 Q0-Q7
VIL VIH X X X DOUT
VIH VIH X X X High Z
X X X X X High Z
VIL VIH VIL VIL VID C2H
VIL VIH VIH VIL VID F9H
VIH VIL X X X DIN
Q8-Q14
HighZ
High Z
HIgh Z
High Z
High Z
High Z
Q15/A-1
VIL/VIH
X
X
VIL
VIL
VIL/VIH
NOTES :
1. X can be VIH or VIL for address or control pins.
2. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes. A0 at VIL, A1 at VIH and
with appropriate sector addresses provide Sector Protect Code.(Refer to Table 4)
3. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully
completed through proper command sequence.
4. VID = 11.5V- 12.5V.
P/N:PM0641
REV. 0.3, NOV. 06, 2001
5
5 Page 
MX29L3211
READ STATUS REGISTER
The MXIC's 32 Mbit flash family contains a status
register which may be read to determine when a program
or erase operation is complete, and whether that
operation completed successfully. The status register
may be read at any time by writing the Read Status
command to the CIR. After writing this command, all
subsequent read operations output data from the status
www.DataSheetr4eUg.cisotmer until another valid command sequence is
written to the CIR. A Read Array command must be
written to the CIR to return to the Read Array mode.
The status register bits are output on Q3 - Q7(table 6)
whether the device is in the byte-wide (x8) or word-wide
(x16) mode for the MX29L3211. In the word-wide mode
the upper byte, Q(8:15) is set to 00H during a Read
Status command. In the byte-wide mode, Q(8:14) are
tri-stated and Q15/A-1 retains the low order address
function. Q0-Q1 is set to 0H in either x8 or x16 mode.
It should be noted that the contents of the status register
are latched on the falling edge of OE or CE whichever
occurs last in the read cycle. This prevents possible bus
errors which might occur if the contents of the status
register change while reading the status register. CE or
OE must be toggled with each subsequent status read,
or the completion of a program or erase operation will not
be evident.
The Status Register is the interface between the
microprocessor and the Write State Machine (WSM).
When the WSM is active, this register will indicate the
status of the WSM, and will also hold the bits indicating
whether or not the WSM was successful in performing
the desired operation. The WSM sets status bits four
through seven and clears bits six and seven, but cannot
clear status bits four and five. If Erase fail or Program fail
status bit is detected, the Status Register is not cleared
until the Clear Status Register command is written. The
MX29L3211 automatically outputs Status Register data
when read after Chip Erase, Sector Erase, Page Program
or Read Status Command write cycle. The default state
of the Status Register after powerup and return from
deep power-down mode is (Q7, Q6, Q5, Q4) = 1000B.
Q3 = 0 or 1 depends on sector-protect status, can not be
changed by Clear Status Register Command or Write
State Machine.
CLEAR STATUS REGISTER
The Erase fail status bit (Q5) and Program fail status bit
(Q4) are set by the write state machine, and can only be
reset by the system software. These bits can indicate
various failure conditions(see Table 6). By allowing the
system software to control the resetting of these bits,
several operations may be performed (such as
cumulatively programming several pages or erasing
multiple blocks in squence). The status register may
then be read to determine if an error occurred during that
programming or erasure series. This adds flexibility to
the way the device may be programmed or erased.
Additionally, once the program(erase) fail bit happens,
the program (erase) operation can not be performed
further. The program(erase) fail bit must be reset by
system software before further page program or sector
(chip) erase are attempted. To clear the status register,
the Clear Status Register command is written to the CIR.
Then, any other command may be issued to the CIR.
Note again that before a read cycle can be initiated, a
Read command must be written to the CIR to specify
whether the read data is to come from the Array, Status
Register or Silicon ID.
P/N:PM0641
REV. 0.3, NOV. 06, 2001
11
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| Páginas | Total 38 Páginas | |
| PDF Descargar | [ Datasheet MX29L3211.PDF ] | |
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