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PDF MX29LA321ML Data sheet ( Hoja de datos )
| Número de pieza | MX29LA321ML | |
| Descripción | 32M-BIT SINGLE VOLTAGE 3V ONLY UNIFORM SECTOR FLASH MEMORY | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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MX29LA321M H/L
FEATURES
GENERAL FEATURES
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program opera-
tions
• Configuration
- 4,194,304 x 8 / 2,097,152 x 16 switchable
• Sector structure
www.DataSheet4U-.c6o4mKB(32KW) x 64
• Latch-up protected to 250mA from -1V to VCC + 1V
• Low VCC write inhibit is equal to or less than 1.5V
• Compatible with JEDEC standard
- Pin-out and software compatible to single power sup-
ply Flash
PERFORMANCE
• High Performance
- Fast access time: 70R/90ns
- Page read time: 25ns
- Sector erase time: 0.5s (typ.)
- 4 word/8 byte page read buffer
- 16 word/ 32 byte write buffer: reduces programming
time for multiple-word/byte updates
• Low Power Consumption
- Active read current: 18mA(typ.)
- Active write current: 20mA(typ.)
- Standby current: 20uA(typ.)
• Minimum 100,000 erase/program cycle
• 20-year data retention
SOFTWARE FEATURES
• Supports Common Flash Interface (CFI)
- Flash device parameters stored on the device and
provide the host system to access.
• Program Suspend/Program Resume
- Suspend program operation to read other sectors
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data/pro-
gram other sectors
• Status Reply
32M-BIT SINGLE VOLTAGE 3V ONLY
UNIFORM SECTOR FLASH MEMORY
- Data# polling & Toggle bits provide detection of pro-
gram and erase operation completion
HARDWARE FEATURES
• Ready/Busy (RY/BY#) Output
- Provides a hardware method of detecting program
and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal
state machine to read mode
• WP#/ACC input
- Write protect (WP#) function allows protection of all
sectors, regardless of sector protection settings
- ACC (high voltage) accelerates programming time
for higher throughput during system
SECURITY
• Sector Protection/Chip Unprotect
- Provides sector group protect function to prevent pro-
gram or erase operation in the protected sector group
- Provides chip unprotect function to allow code
changes
• Sector Permanent Lock
- Through a unique permanent locking scheme, the
device allows the user to permanently lock any ran-
domly selected sector(s) within the memory array
(Please contact Macronix for specifics relating to
this feature - this datasheet does not include any
other information relating to this feature)
• Secured Silicon Sector
- Provides a 128-word OTP area for permanent, se-
cure identification
- Can be programmed and locked at factory or by cus-
tomer
PACKAGE
• 56-pin TSOP
• 64-ball CSP
• All Pb-free devices are RoHS Compliant
GENERAL DESCRIPTION
The MX29LA321M H/L is a 32-mega bit Flash memory
organized as 4M bytes of 8 bits or 2M words of 16 bits.
MXIC's Flash memories offer the most cost-effective and
reliable read/write non-volatile random access memory.
The MX29LA321M H/L is packaged in 56-pin TSOP and
64-ball CSP. It is designed to be reprogrammed and
erased in system or in standard EPROM programmers.
The standard MX29LA321M H/L offers access time as
fast as 70ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the MX29LA321M H/L has separate chip enable
P/N:PM1145
REV. 1.0, FEB. 27, 2006
1
1 page  
BLOCK DIAGRAM
MX29LA321M H/L
CE#
OE#
WE#
www.DataSheet4U.com WP#
BYTE#
RESET#
CONTROL
INPUT
LOGIC
A0-A21
ADDRESS
LATCH
AND
BUFFER
Q0-Q15
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
FLASH
ARRAY
Y-PASS GATE
ARRAY
SOURCE
HV
SENSE PGM
AMPLIFIER DATA
HV
PROGRAM
DATA LATCH
STATE
REGISTER
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
P/N:PM1145
REV. 1.0, FEB. 27, 2006
5
5 Page 
MX29LA321M H/L
REQUIREMENTS FOR READING ARRAY
DATA
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at VIH.
The internal state machine is set for reading array data
www.DataSheetu4pUo.cnomdevice power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid address on
the device address inputs produce valid data on the de-
vice data outputs. The device remains enabled for read
access until the command register contents are altered.
PAGE MODE READ
The MX29LA321M H/L offers "fast page mode read" func-
tion. This mode provides faster read access speed for
random locations within a page. The page size of the
device is 4 words/8 bytes. The appropriate page is se-
lected by the higher address bits A1~A2(Word Mode)/
A0~A2(Byte Mode) This is an asynchronous operation;
the microprocessor supplies the specific word location.
The system performance could be enhanced by initiating
1 normal read and 3 fast page read (for word mode A1-
A2) or 7 fast page read (for byte mode A0~A2). When
CE# is deasserted and reasserted for a subsequent ac-
cess, the access time is tACC or tCE. Fast page mode
accesses are obtained by keeping the "read-page ad-
dresses" constant and changing the "intra-read page"
addresses.
WRITING COMMANDS/COMMAND SE-
QUENCES
To program data to the device or erase sectors of memory,
the system must drive WE# and CE# to VIL, and OE# to
VIH.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Table on
page 6 and 7 indicates the address space that each
sector occupies. A "sector address" consists of the ad-
dress bits required to uniquely select a sector.The "Writ-
ing specific address and data commands or sequences
into the command register initiates device operations.
Table 3 defines the valid register command sequences.
Writing incorrect address and data values or writing them
in the improper sequence resets the device to reading
array data. Section has details on erasing a sector or the
entire chip, or suspending/resuming the erase operation.
After the system writes the Automatic Select command
sequence, the device enters the Automatic Select mode.
The system can then read Automatic Select codes from
the internal register (which is separate from the memory
array) on Q7-Q0. Standard read cycle timings apply in
this mode. Refer to the Automatic Select Mode and Au-
tomatic Select Command Sequence section for more
information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The "AC
Characteristics" section contains timing specification
table and timing diagrams for write operations.
WRITE BUFFER
Write Buffer Programming allows the system to write a
maximum of 16 words/32 bytes in one programming op-
eration.This results in faster effective programming time
than the standard programming algorithms. See "Write
Buffer" for more information.
ACCELERATED PROGRAM OPERATION
The device offers accelerated program operations through
the ACC function. This is one of two functions provided
by the ACC pin. This function is primarily intended to
allow faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors, and
uses the higher voltage on the pin to reduce the time
required for program operations. The system would use
a two-cycle program command sequence as required by
the Unlock Bypass mode. Removing VHH from the ACC
pin must not be at VHH for operations other than accel-
erated programming, or device damage may result.
P/N:PM1145
REV. 1.0, FEB. 27, 2006
11
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