DataSheet.jp

8272 の電気的特性と機能

8272のメーカーはIntel Corporationです、この部品の機能は「Single / Double Density Floppy Disk Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 8272
部品説明 Single / Double Density Floppy Disk Controller
メーカ Intel Corporation
ロゴ Intel Corporation ロゴ 




このページの下部にプレビューと8272ダウンロード(pdfファイル)リンクがあります。

Total 27 pages

No Preview Available !

8272 Datasheet, 8272 PDF,ピン配置, 機能
Visit Intel's WWW site for more information on recent products and services.
8272
SINGLE/DOUBLE DENSITY
FLOPPY DISK CONTROLLER
&amstrad;
IBM Compatible in Both Single and Double Density Recording Formats
Programmable Data Record Lengths: 128,256,512, or 1024 Bytes/Sector
www.DataSheetM4Uu.clotmi-Sector and Multi-Track Transfer Capability
Drive up to 4 Floppy Disks
Data Scan Capability - Will Scan a Single Sector or an Entire Cylinder's Worth of Data
Fields, Comparing on a Byte by Byte Basis, Data in the Processor's Memory with Data
Read from the Diskette
Data Transfers in DMA or Non-DMA Mode
Parallel Seek Operations on Up to Four Drives
Compatible with Most Microprocessors including 8080A,8085A,8086 and 8088
Single-Phase 8 Mhz Clock
Single +5 Volt Power Supply
Available in 40-Pin Plastic Dual-in-Line Package
The 8272 is a LSI Floppy Disk Controller (FDC) Chip, which contains the curcuitry and control
functions for interfacing a processor to 4 Floppy Disk Drives. It is capable of supporting either
IBM 3740 single density format (FM), or IBM System 34 Double Density format (MFM) including
double sided recording. The 8272 provides control signals which simplify the design of an
external phase locked loop, and write precompensation circuitry. The FDC simplifies and
handles most of the burdens associated with implementing a Floppy Disk Drive Interface.
PIN CONFIGURATION

1 Page





8272 pdf, ピン配列
DESCRIPTION
Hand-shaking signals are provided in the 8272 which make DMA operation easy to incorporate
with the aid of an external DMA controller chip, such as the 8237. The FDC will operate in
either DMA or Non-DMA mode. In the Non-DMA mode, the FDC generates interrupts to the
processor for every transfer of a data byte between the CPU and 8272. In the DMA mode, the
processor need only to load a command into the FDC and all data transfers occur under
control of the 8272 and DMA controller.
There are 15 seperate commands which the 8272 will execute. Each of these commands
require multiple 8-bit bytes to fully specify the operation which the processor wishes the FDC
to perform. The following commands are available.
www.DataSheet4U.com
Read Data
Read ID
Read Deleted Data
Read a Track
Scan Equal
Scan High or Equal
Scan Low or Equal
Specify
Write Data
Format a Track
Write Deleted Data
Seek
Recalibrate (Restore to
track 0)
Sense Interrupt Status
Sense Drive Status
FEATURES
Address mark detection curcuitry is internal to the FDC which simplifies the phase locked loop
and read electronics. The track stepping rate, head load time, and head unload time may be
programmed by the user. The 8272 offers many additional features such as multiple sector
transfers in both read and write modes with a single command, and full IBM compatibility in
both single (FM) and double density (MFM) modes.
8272 REGISTERS - CPU INTERFACE
The 8272 contains two registers which may be accessed by the main system processor, a
Status Register and a Data Register. The 8-bit Main Status Register contains the status
information of the FDC, and may be accessed at any time. The 8-bit Data Register (actually
consists of several registers in a stack with only one register presented to the data bus at a
time), stores data, commands, parameters, and FDD status information. Data bytes are read
out of, or written into, the Data Register in order to program or obtain the results after
execution of a command. The Status Register may only be read and is used to facilitate the
transfer of data between the processor and the 8272.
The relationship between the Status/Data registers and the signals /RD,/WR and A0 is shown
below.
A0 /RD /WR
FUNCTION
0 0 1 Read Main Status Register
0 1 0 Illegal


3Pages


8272 電子部品, 半導体
37 FR/STP O
36 HDL
O
35 RDY
I
34
www.DataSheet4U.com
WP/TS
I
33 FLT/TRK0 I
31,32 PS1,PS0 O
30 WR DATA O
28,29 DS1,DS0 O
27 HDSEL O
26 MFM
25 WE
24 VCO
O
O
O
23 RD DATA I
22 DW
I
21 WR CLK I
FDD
FDD
FDD
FDD
FDD
FDD
FDD
FDD
FDD
PLL
FDD
PLL
FDD
PLL
step pulses to move head to
another cylinder in seek
mode.
Head Load: Command
which causes read/write
head in FDD to contact
diskette.
Ready: Indicates FDD is
ready to send or receive
data.
Write Protect/Two Side:
Senses Write Protect status
in Read/Write mode and
Two side media in Seek
mode.
Fault/Track 0: Senses FDD
fault condition in Read/Write
mode and Track 0 condition
in Seek mode.
Precompensation (pre-
shift): Write
precompensation status
during MFM mode.
Determines early, late and
normal times.
Write data: Seial clock and
data bits to FDD.
Drive Select: Selects FDD
unit
Head Select: Head 1
selected when "1" (high).
Head 0 selected when
"0" (low).
MFM Mode: MFM mode
when "1", FM mode when
"0"
Write Enable: Enables write
data into FDD
VCO Sync: Inhibits VCO in
PLL when "0" (low), enables
VCO when "1".
Read Data: Read data from
FDD containing clock and
data bits
Data window. Generated by
PLL, and used to sample
data from FDD
Write Clock: Write data rate
to FDD FM = 500Khz, MFM
= 1 Mhz, with a pulse width
of 250ns for both FM and

6 Page



ページ 合計 : 27 ページ
 
PDF
ダウンロード
[ 8272 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
8272

Single / Double Density Floppy Disk Controller

Intel Corporation
Intel Corporation
8272A

Single / Double Density Floppy Disk Controller

Intel Corporation
Intel Corporation
8273

Programmable HDLC/SDLC Protocol Controller

Intel
Intel
82731

Video Interface Controller

Intel
Intel


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap